EFM32WG890 Datasheet, PDF (55/85 Pages) Silicon Laboratories – Operation from backup battery when main power drains out

Table 3.28. I2C Fast-mode Plus (Fm+)
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Symbol
Parameter
Min
Typ
Max
Unit
f_SCL
SCL clock frequency
0
1000¹ kHz
t_LOW
SCL clock low time
0.5
µs
t_HIGH
SCL clock high time
0.26
µs
t_SU,DAT
SDA set-up time
50
ns
t_HD,DAT
SDA hold time
8
ns
t_SU,STA
Repeated START condition set-up time
0.26
µs
t_HD,STA
(Repeated) START condition hold time
0.26
µs
t_SU,STO
STOP condition set-up time
0.26
µs
t_BUF
Bus free time between a STOP and a START condi-
0.5
µs
tion
1_{For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32WG Reference Manual.}
3.18 USART SPI
Figure 3.43. SPI Master Timing
CS
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
MOSI
MISO
t _{CS_MO}
t _{SCKL_MO}
t _SCLK
t _{SU_MI}
t _{H_MI}
Table 3.29. SPI Master Timing
Symbol
Parameter
Condition
Min
Typ
t_SCLK ^{1 2}
SCLK period
2 * t_HFPER-
CLK
t_{CS_MO} ^{1 2}
CS to MOSI
-2.00
t_{SCLK_MO} ^{1 2}
SCLK to MOSI
-1.00
t_{SU_MI} ^{1 2}
MISO setup time IOVDD = 3.0 V
36.00
t_{H_MI} ^{1 2}
MISO hold time
-6.00
1_{Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)}
2_{Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)}
Max
Unit
ns
2.00 ns
3.00 ns
ns
ns
2014-06-13 - EFM32WG890FXX - d0198_Rev1.40
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