EFM32WG290 Datasheet, PDF (53/82 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

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Symbol
Parameter
t_{H_ARDY} ^{1 2 3 4}
Hold time, from trailing EBI_REn, EBI_WEn edge
to EBI_ARDY invalid
1_{Applies for all addressing modes (figure only shows D16A8.)}
2_{Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn)}
3_{Applies for all polarities (figure only shows active low signals)}
4_{Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)}
Min
Typ
-1 + (3 * t_HFCORECLK)
Max
3.16 I2C
Unit
ns
Table 3.25. I2C Standard-mode (Sm)
Symbol
Parameter
Min
Typ
Max
Unit
f_SCL
SCL clock frequency
0
100¹ kHz
t_LOW
SCL clock low time
4.7
µs
t_HIGH
SCL clock high time
4.0
µs
t_SU,DAT
t_HD,DAT
SDA set-up time
SDA hold time
250
ns
8
3450^2,3 ns
t_SU,STA
Repeated START condition set-up time
4.7
µs
t_HD,STA
(Repeated) START condition hold time
4.0
µs
t_SU,STO
STOP condition set-up time
4.0
µs
t_BUF
Bus free time between a STOP and a START condi-
4.7
µs
tion
1_{For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32WG Reference Manual.}
2_{The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).}
3_{When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10}-9 _{[s] * fHFPERCLK [Hz]) - 4).}
Table 3.26. I2C Fast-mode (Fm)
Symbol
Parameter
Min
Typ
Max
Unit
f_SCL
SCL clock frequency
0
400¹ kHz
t_LOW
SCL clock low time
1.3
µs
t_HIGH
SCL clock high time
0.6
µs
t_SU,DAT
t_HD,DAT
SDA set-up time
SDA hold time
100
ns
8
900^2,3 ns
t_SU,STA
Repeated START condition set-up time
0.6
µs
t_HD,STA
(Repeated) START condition hold time
0.6
µs
t_SU,STO
STOP condition set-up time
0.6
µs
t_BUF
Bus free time between a STOP and a START condi-
1.3
µs
tion
1_{For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32WG Reference Manual.}
2_{The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).}
3_{When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10}-9 _{[s] * fHFPERCLK [Hz]) - 4).}
2014-06-13 - EFM32WG290FXX - d0188_Rev1.40
53
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