EM3591 Datasheet, PDF (50/59 Pages) Silicon Laboratories – High-Performance, Integrated ZigBee

EM359x
Table 6.1. EM359x Pin Descriptions (Continued)
Pin #
Signal
Direction
Description
43
PB0
I/O Digital I/O
VREF
VREF
IRQA
Analog O ADC reference output
Enable analog function with GPIO_PBCFGL[3:0]
Analog I ADC reference input
Enable analog function with GPIO_PBCFGL[3:0]
Enable reference output with an Ember system function
I
External interrupt source A
TRACEDATA2
O
Synchronous CPU trace data bit 2
(see also Pin 30)
Select 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PBCFGL[3:0]
TIM1CLK
I
Timer 1 external clock input
TIM2MSK
I
Timer 2 external clock mask input
44
VDD_PADS
Power Pads supply (2.1–3.6 V)
45
PC1
I/O Digital I/O
ADC3
Analog ADC Input 3
Enable analog function with GPIO_PCCFGL[7:4]
TRACEDATA3
O
Synchronous CPU trace data bit 3
(see also Pin 31)
Select 1-, 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[7:4]
46
VDD_MEM
Power 1.8 V supply (flash, RAM)
47
PC0
I/O Digital I/O
High Either enable with GPIO_DBGCFG[5],
current or enable Serial Wire mode (see JTMS description, Pin 42) and disable
TRACEDATA1
JRST
IRQD¹
I
JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS description, 
Pin 42) and TRACEDATA1 is disabled
Internal pull-up is enabled
I
Default external interrupt source D.
TRACEDATA1
O
Synchronous CPU trace data bit 1
Select 2- or 4-wire synchronous trace interface in ARM core
Enable trace interface in ARM core
Select alternate output function with GPIO_PCCFGL[3:0]
Note:
1. IRQC and IRQD external interrupts can be mapped to any digital I/O pin using the GPIO_IRQCSEL and
GPIO_IRQDSEL registers.
50
Rev 1.0