EFM32GG280 Datasheet, PDF (46/78 Pages) Silicon Laboratories – Memory Protection Unit

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Figure 3.30. EBI Read Enable Related Output Timing
EBI_BL[ 1 : 0 ]
EBI_A[ 2 7 : 0 ]
EBI_AD[ 1 5 : 8 ]
EBI_CSn
EBI_AD[ 7 : 0 ]
EBI_REn
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_BL
t _{SU_REn}
Z
t _{H_REn}
EBI_A
t _{SU_REn}
Z
t _{H_REn}
ADDR[ 7 : 0 ]
t _{SU_REn}
Z
t _{H_REn}
t _{SU_REn}
Z
DATA[7:0]
t _{H_REn}
Z
t _{WIDTH_REn}
Table 3.22. EBI Read Enable Related Output Timing
Symbol
Parameter
Min
Typ Max Unit
t_{OH_REn} ^{1 2 3 4}
Output hold time, from trailing EBI_REn/
-10.00 + (RDHOLD *
ns
EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn,
t_HFCORECLK)
EBI_BLn invalid
t_{OSU_REn} ^{1 2 3 4 5}
Output setup time, from EBI_AD, EBI_A, EBI_CSn, -10.00 + (RDSETUP
ns
EBI_BLn valid to leading EBI_REn/EBI_NANDREn
* t_HFCORECLK)
edge
t_{WIDTH_REn} ^{1 2 3 4 5 6} EBI_REn pulse width
-9.00 + ((RD-
ns
STRB+1) * t_HFCORE-
CLK⁾
1_{Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing}
modes D8A24ALE and D16A16ALE)
2_{Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)}
3_{Applies for all polarities (figure only shows active low signals)}
4_{Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)}
5_{The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge}
of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of t_{WIDTH_REn} and increases the length
of t_{OSU_REn} by 1/2 * t_HFCLKNODIV.
6_{When page mode is used, RDSTRB is replaced by RDPA for page hits.}
2014-05-23 - EFM32GG280FXX - d0036_Rev1.30
46
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