SI533 Datasheet, PDF (4/12 Pages) Silicon Laboratories – DUAL FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Si533
Table 4. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)*
for F_OUT > 500 MHz
Phase Jitter (RMS)*
for F_OUT of 125 to 500 MHz
Symbol
Test Condition
Min
φ_J
12 kHz to 20 MHz (OC-48)
—
50 kHz to 80 MHz (OC-192)
—
φ_J
12 kHz to 20 MHz (OC-48)
—
50 kHz to 20 MHz (OC-192)
—
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
Typ
0.25
0.26
0.36
0.34
Max
0.40
0.37
0.50
0.42
Units
ps
ps
Table 5. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Period Jitter*
J_PER
RMS
Peak-to-Peak
—
2
—
ps
—
14
—
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. CLK± Output Phase Noise (Typical)
Offset Frequency (f)
120.00 MHz
LVDS
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
156.25 MHz
LVPECL
–105
–122
–128
–135
–144
–147
n/a
622.08 MHz
LVPECL
–97
–107
–116
–121
–134
–146
–148
Units
dBc/Hz
4
Rev. 1.1