AN851 Datasheet, PDF (4/25 Pages) Silicon Laboratories – Si468X SCHEMATICS AND LAYOUT GUIDE

AN851
3.2.1. Component Selection and Replacement
The front end network components shall be placed as close as possible to the chip and as far away from noise
sources such as clocks and digital circuits. L1 shall be routed to ground plane with a short trace and a via
connection.
The recommendations regarding C1, C2, C3, C5, C6, C7, C8, C9 and C10 are made to reduce the size of the
current loop created by the bypass cap and routing, minimize impedance and return all currents to the ground.
C3 and C4 (2.2 nF and 1 uF) are required bypass capacitors for VA supply pin 12. Place C2, C3 and C4 as close
as possible to VA. C3 and C4 are chosen to mitigate noise in medium to VHF frequency range. Place a via
connecting C2, C3, C4 and VA pins to the power rail such that the caps are closer to the Si468x VA pin than the via.
Route C2, C3 and C4 only to the ABYP pin directly with a short (6-mil width) low inductance trace.
C9 and C22 (2.2 nF and 1 uF) are required bypass capacitors for VIO supply pin 34. C9 and C22 are chosen to
mitigate noise in medium to VHF frequency range. Place C6, C9, and C22 as close as possible to VIO pin 34 and
DBYP pin 36. Place a via connecting C6, C9, and C22 and VIO supply to the power rail such that the caps are
closer to the Si468x VIO pin than the via. Route C6, C9, and C22 only to DBYP pin directly with a short (6-mil
width) low inductance trace.
C10 and C23 (2.2nF and 1 uF) are required bypass capacitors for VMEM supply pin 35. C10 and C23 are chosen
to mitigate noise in medium to VHF frequency range. Place C7, C10, and C23 as close as possible to VMEM pin
35 and DBYP pin 36. Place a via connecting C7, C10, and C23 and VMEM supply pin to the power rail such that
the caps are closer to the Si468x VMEM pin than the via. Route C7, C10, and C23 only to DBYP pin directly with a
short (6-mil width) low inductance trace.
C11 and C24 (2.2nF and 1 uF) are required bypass capacitors for VCORE supply pin 37. C11 and C24 are chosen
to mitigate noise in medium to VHF frequency range. Place C8, C11 and C24 as close as possible to VCORE pin
37 and DBYP pin 36. Place a via connecting C8, C11 and C24 and VCORE pin 37 to the power rail such that the
caps are closer to the Si468x VCORE pin than the via. Route C8, C11 and C24 only to DBYP directly with a short
(6-mil width) low inductance trace.
C5 (1uF) is an optional bypass capacitor for DACREF pin 17 if customer uses analog audio output. Place C4 as
close as possible to DACREF pin. Customers do not need to populate this capacitor if they are using digital audio
output only.
C20 and C21 (1uF) are optional ac coupling capacitors for analog audio outputs. The value should be selected to
work well with the customer’s choice of audio amp.
X1 is an optional crystal required only when using the internal oscillator feature. Place the crystal X1 as close to
XTALI (pin 15) and XTALO (pin 16) as possible to minimize current loops.
3.3. Layout Guide
The following placement/layout guidelines are suggested for 4-layer PCB:
PCB layer assignment:
Layer 1 top side placement and routing for RF and analog traces
Layer 2 ground plane
Layer 3 routing for high frequency digital traces and ground plane
Layer 4 bottom side placement and routing for low frequency digital traces
Minimum 6-mil trace
Minimum 6-mil trace spacing
6-mil drill 9-mil plating for normal vias
Minimum 10-mil component spacing
Power routed by trace
0402 component size or larger
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