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EFM32HG322 Datasheet, PDF (33/70 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode
Preliminary
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Symbol
IADCREF
CADCIN
RADCIN
RADCFILT
CADCFILT
fADCCLK
Parameter
Condition
Min
MODE in ADCn_CTRL set to
0b11
Current consump-
tion of internal volt-
age reference
Internal voltage reference
Input capacitance
Input ON resistance
Input RC filter resis-
tance
Input RC filter/de-
coupling capaci-
tance
ADC Clock Fre-
quency
6 bit
tADCCONV
8 bit
Conversion time
12 bit
tADCACQ
Acquisition time
Programmable
tADCACQVDD3
tADCSTART
SNRADC
Required acquisi-
tion time for VDD/3
reference
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
Startup time of ref-
erence generator
and ADC core in
KEEPADCWARM
mode
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
Signal to Noise Ra-
tio (SNR)
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
Typ
1
7
11
13
1
2
Max
Unit
65
µA
2
pF
MOhm
10
kOhm
250
fF
13 MHz
ADC-
CLK
Cycles
ADC-
CLK
Cycles
ADC-
CLK
Cycles
256 ADC-
CLK
Cycles
µs
5
µs
1
µs
59
dB
63
dB
65
dB
60
dB
65
dB
54
dB
2015-05-06 - EFM32HG322FXX - _Rev0.91
33
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