SI4313 Datasheet, PDF (32/52 Pages) Silicon Laboratories – Si4313 LOW-COST ISM RECEIVER

Si4313-B1
8. Auxiliary Functions
8.1. Smart Reset
The Si4313 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector, POR. This reset circuit was designed to produce a reliable
reset signal under any circumstances. Reset will be initiated if any of the following conditions occurs:
 Initial power on, VDD starts from GND: reset is active till VDD reaches VRR (see table).
 When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR.
 A software reset via Register 08h. "Operating Mode and Function Control 2," where reset is active for time
TSWRST.
 On the rising edge of a VDD glitch when the supply voltage exceeds the time functioned limit of Figure 10.
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
0.4V
actual VDD(t)
showing glitch
t=0,
VDD starts to rise
Reset
T_P
t
reset:
Vglitch>=0.4+t*0.2V/ms
Figure 10. POR Glitch Parameters
Table 13. POR Parameters
Parameter
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
Software Reset Pulse
Threshold Voltage
Reference Slope
VDD Glitch Reset Pulse
Symbol
Comment
Min Typ Max Unit
VRR
0.85 1.3 1.75 V
SVDD
Tested VDD Slope Region
0.03
300 V/ms
VLD
VLD<VRR
0.7
1
1.3
V
T_SWRST
VTSD
50
470 µs
0.4
V
K
0.2
V/ms
TP
Also occurs after SDN, and initial
power on
5
16
40
ms
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
32
Rev. 0.5