SI5374B-A-GL Datasheet, PDF (3/20 Pages) Silicon Laboratories – Timing Selector Guide

CLOCK AND OSCILLATOR SELECTOR / 3
Clock Generation
WEB-CONFIGURABLE FACTORY-CUSTOMIZED CLOCK GENERATORS AVAILABLE AT: www.silabs.com/custom-timing
Any-Frequency, Any-Output Differential/CMOS Clocks
Silicon Labs’ differential + LVCMOS clock generators provide any rate, any output frequency synthesis. Any
combination of output frequencies can be generated exactly with 0 ppm error. Independent signal format and
VDDO options provide integrated level translation, supporting LVPECL/LVDS/HCSL/LVCMOS clock generation up
to 710 MHz with sub 1 ps rms phase jitter.
Si5338 FEATURES
• Generates any frequency on any output, from 160 kHz
  to 350 MHz and select frequencies to 710 MHz
• Exact clock synthesis (0 ppm error)
• Crystal or clock input
• 4 differential outputs or 8 single-ended outputs
• Any format, on any output: LVPECL, LVDS, HCSL,
 LVCMOS, HSTL, SSTL and CML
• Independent VDDO per output eliminates external
  level translators (1.5, 1.8, 2.5, 3.3 V)
• Low phase jitter: 1 ps rms
• I²C programmable or pin-controlled
• Excellent PSRR, no discrete components
• Spread spectrum clock generation
• User-definable control pins: Powerdown,
  Output Enable, Frequency Select, Spread Select
• Factory-customizable clocks w/2 week lead times
www.silabs.com/custom-timing
25 MHz
Si5338
SCi5lo3c3k 5/38
Generator
25 MHz 1.8 V CMOS
25 MHz 1.8 V CMOS
66.6 MHz ±5% 3.3 V CMOS
100 MHz 2.5 V LVPECL
1.544 MHz/2.048 MHz 3.3 V CMOS
GbE
Ethernet
PHY
GbE
Ethernet
PHY
µProcessor
FPGA
T1/E1
Framer
PART NUMBER
CONTROL
CLOCK
INPUT/
OUTPUTS
INPUT
FREQUENCY (MHZ)
Si5334
Pin
1/4
5 - 710 (Clock),
8 - 30 (Xtal)
Si5335
Pin
1/4
10 - 350 (Clock),
25/27 (Xtal)
Si5338
I²C
1/4
5 - 710 (Clock),
8 - 30 (Xtal)
OUTPUT
FREQUENCY (MHZ)
0.16 - 710 MHz
0.16 - 350 MHz
0.16 - 200 MHz
1 - 350 MHz
0.16 - 710 MHz
0.16 - 350 MHz
0.16 - 200 MHz
PHASE
JITTER
(RMS)
VDD
VDDO
1.0 ps 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V
1.0 ps 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V
1.0 ps 1.8, 2.5, 3.3 V 1.8, 2.5, 3.3 V
OUTPUT
PACK AGE
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL, CML
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL, CML
QFN24
QFN24
QFN24