SI535X-24QSOP-EVB Datasheet, PDF (3/14 Pages) Silicon Laboratories – Fully-powered from a single USB port

Si535x-24QSOP-EVB
2. Jumpers
The following jumpers are available on the evaluation board:
 VDD—Connects the Si5350/51 pin to the VDD voltage regulator (normally installed).
 VDD VOLT_SEL—Allows user to select a VDD voltage of 2.5 V or 3.3 V (default 3.3 V).
 VDDOA—Connects the Si5350/51 pin to the VDDOA voltage regulator (normally installed).
 VDDOA VOLT_SEL—Allows user to select a VDDOA voltage of 2.5 V or 3.3 V (default 3.3 V).
 VDDOB—Connects the Si5350/51 pin to the VDDOB voltage regulator (normally installed).
 VDDOB VOLT_SEL—Allows user to select a VDDOB voltage of 2.5 V or 3.3 V (default 3.3 V).
 VDDOC—Connects the Si5350/51 pin to the VDDOC voltage regulator (normally installed).
 VDDOC VOLT_SEL—Allows user to select a VDDOC voltage of 2.5 V or 3.3 V (default 3.3 V).
 VDDOD—Connects the Si5350/51 pin to the VDDOD voltage regulator (normally installed).
 VDDOD VOLT_SEL—Allows user to select a VDDOD voltage of 2.5 V or 3.3 V (default 3.3 V).
 SCL—Connects the Si5350/51 SCL pin to the I²C bus from the MCU. Removing the jumper breaks the
connection to the MCU and allows the user to feed in an external I²C signal to the device.
 SDA—Connects the Si5350/51 SDA pin to the I²C bus from the MCU. Removing the jumper breaks the
connection to the MCU and allows the user to feed in an external I²C signal to the device.
 EXP POWER—Allows user to select between 5 V USB supply and 5 V external supply on J17. See Figure 1 for
jumper locations.
3. Status LEDs
There are three status LEDs on the evaluation board:
 RDY (Green)—Indicates that the EVB is operating normally. This LED should always be on.
 BUSY (Green)—Indicates that the on-board MCU is communicating with the device and/or the USB host.
 INTR (Red)—Indicates device or EVB fault condition (also on when DUT hasn't been programmed).
4. Clock Inputs
The EVB can operate in asynchronous mode using the onboard 27 MHz crystal, in synchronous mode using an
external CMOS clock source, or in both modes if both PLLs in the device are utilized. An SMA connector is
provided to interface an external clock source to CLKIN. Additionally, CLKIN can be applied using the test hooks
TP39/TP49.
Preliminary Rev. 0.2
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