SI5320-EVB Datasheet, PDF (3/18 Pages) List of Unclassifed Manufacturers – EVALUATION BOARD FOR Si5320 SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5320-EVB
and a 0.1 F capacitor, such that the positive and
negative inputs of the differential pair each see a 50 
termination to “ac ground,” and the line-to-line
termination impedance is 100 .
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
For single-ended operation, supply a signal to one of
the differential inputs (usually the positive input). The
other input should be shorted to ground using an SMA
shorting plug. The on-board termination circuit provides
a 50  termination to ac-ground for each leg of the
differential pair.
Differential Clock Output Signals
The differential clock outputs from the Si5320 device
are routed to the perimeter of the circuit board using
50  transmission line structures. The capacitors that
provide ac-coupling are located near the clock output
SMA connectors.
Internal Regulator Compensation
The Si5320-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0  resistor. The
capacitor pads are populated with a low ESR 33 F
tantalum capacitor. This is the suggested compensation
circuit for Si5320 devices.
The acceptable range for the time constant at this node
is 15 s to 50 s. The capacitor used on the board is a
33 F capacitor with an ESR of .8 . This yields a time
constant of 26.4 s. The designer could decide to use a
330 F capacitor with an ESR of .15 . This yields a
time constant of 49.5 s. Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330 F case provides greater
noise filtering. However, the large case size of the
330 F capacitor might make it impractical for many
applications. The Si5320 device is specified with the
33 F cap.
Default Jumper Settings
The default jumper settings for the Si5320-EVB board
are given in Table 1. These settings configure the board
for operation from a 3.3 V supply.
Table 1. Si5320-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
JP6
JP1
JP5
JP7
Signal
VSEL33
VDD33
VALTIME
FEC[0]
FEC[1]
BWSEL[0]
BWSEL[1]
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
FRQSEL[0]
FRQSEL[1]
DBLBW
FXDDELAY
LED ENABLE
State
1
Open
0
0
0
0
1
1
0
0
1
1
1
0
On
Notes
Internal Regulator enabled
3.3 V plane not connected to 2.5 V plane
100 ms Validation Time
No FEC scaling
No FEC scaling
Loop Filter Bandwidth = 800 Hz
Loop Filter Bandwidth = 800 Hz
Clock IN = 19.44 MHz
Clock IN = 19.44 MHz
Clock IN = 19.44 MHz
Clock Out = 622.08 MHz
Clock Out = 622.08 MHz
Selected bandwidth not doubled
Fixed Delay disabled
LED Indicators enabled
Rev. 0.4
3