AN671 Datasheet, PDF (3/6 Pages) STMicroelectronics – Prevention of Data Corruption in ST6 On-Chip EEPROM

AN671
3.1. Crossbar Functionality on Reset
After a device reset, all crossbars enter a disabled default reset state. Port Bank pins connected to a disabled
crossbar are forced into a high impedance digital input mode. Firmware must enable the crossbar associated with
a specific Port Bank pin in order to use that pin as an output. In most applications, firmware will enable all
crossbars on the device to control all the available I/O pins on the device.
When a crossbar is enabled with no internal signals selected to be routed to I/O pins, the crossbar provides full
general purpose input/output (GPIO) access to the Port Banks associated with it. Pins with full GPIO access can
be used as digital inputs, digital outputs, or may be used by various analog functions on the device. As internal
signals are selected to be routed to I/O pins (or “enabled in the crossbar”), the crossbar claims pins from the
associated port banks. Pins claimed by the crossbar cannot be used as GPIO and are under the full control of the
crossbar and the associated peripheral.
3.2. Skipping Pins in the Crossbar
The crossbars have a pin-skipping feature for pins that must be reserved GPIO or analog functions. Any Port Bank
pin with its corresponding PBSKIPEN bit set to 1 cannot be claimed by the crossbar and will remain available for
GPIO or analog functions. The ability to have the crossbar skip certain pins is useful when a system designer is
trying to achieve a specific pinout for the device.
3.3. Crossbar Priority Order
As internal signals are enabled in a crossbar, the crossbar claims pins from the Port Banks to connect to the
internal signal, starting with the least significant Port Bank pin and finishing with the most significant Port Bank pin.
As an example, crossbar 0 of SiM3U1xx devices would start with PB0.0, then PB0.1, and continue in this fashion
until reaching PB1.15. If the crossbar encounters a pin that has its PBSKIPEN bit set to 1, it skips over the pin and
claims the next available pin. Any pin not claimed by the crossbar can be used for GPIO or analog functions.
The crossbar uses a priority order to assign enabled internal signals to claimed Port Bank pins. This priority order
varies with the specific crossbar implementation. Figure 3 shows an example priority order from crossbar 0 of
SiM3U1xx devices. In this example, there are four enabled peripherals that require pin assignment: SPI0, EPCA0,
UART0, and UART1. From the enabled peripherals, SPI0 has the highest priority, so it will be assigned to the first
three pins claimed by the crossbar. Note that in this example configuration, firmware configured the first 8 pins of
PB0 (PB0.0 - PB0.7) to be skipped by the crossbar; the crossbar will assign the SPI0 pins to PB0.8, PB0.9, and
PB0.10. Following the priority order, the EPCA0 pins are assigned to PB0.11, PB0.12, PB0.15, PB1.0. The PB1.2.
PB0.13 and PB0.14 pins are not assigned to EPCA0 because they are configured to be skipped by the crossbar.
UART0 and UART1 are assigned to the next four available pins: PB1.3, PB1.4, PB.15, and PB1.6. The remaining
pins (PB1.7–PB1.15) are not claimed by the crossbar.
3.4. Creating a Flexible Device Pinout
The definition of a system can sometimes change in the middle of the design cycle, necessitating a pinout change.
Planning ahead for such changes in pinout can save costly PCB revisions and decrease time to market when a
system definition change does occur. In the example pinout shown in Figure 3, SPI0 is used in 3-wire mode. If the
communication protocol was changed from 3-wire to 4-wire mode, then PB0.11 would be used for the NSS signal,
causing all peripherals of lower priority order to shift by one pin. Using the crossbar’s skip functionality, the system
designer can plan ahead for such a change by skipping PB0.11 when the specification calls for 3-wire SPI mode.
The skipped pin can later be un-skipped if the specification later requires the use of 4-wire SPI without affecting the
location of peripherals with a lower priority order. If the specification does not change, the skipped pin can be used
for GPIO (e.g., to control an LED or as a debug signal). Adding a few skipped pins when determining the original
device pinout can allow future functionality to be added with minimal impact on the device pinout.
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