SI4455 Datasheet, PDF (27/40 Pages) Silicon Laboratories – 20-Pin 3x3 mm QFN package

Si4455
5.2.5. Power on Reset
A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this
process, VDD must ramp within 1 ms and must remain applied to the device for at least 10 ms. If VDD is removed,
then it must stay below 0.15 V for at least 10 ms before being applied again. Refer to Figure 14 and Table 13 for
details.
Figure 14. POR Timing Diagram
Table 13. POR Timing
Variable
Description
t_PORH
t_PORL
V_RRH
V_RRL
t_SR
High time for VDD to fully settle POR circuit.
Low time for VDD to enable POR.
Voltage for successful POR.
Starting Voltage for successful POR.
Slew rate of VDD for successful POR.
Min
Typ
10
10
90%*Vdd
0
Max Units
ms
ms
V
150 mV
1
ms
Rev 1.1
27