SI2107_06 Datasheet, PDF (26/94 Pages) Silicon Laboratories – SATELLITE RECEIVER FOR DVB-S/DSS WITH QUICKLOCK AND QUICKSCAN

Si2107/08/09/10
In legacy mode, seven different carrier offset estimation
search range scans can be programmed from 0.10 to
~6.0 MHz with register CESR. This mode locates
frequency offsets when the carrier falls within the offset
search range. Smaller search ranges result in faster
search times.
In QuickLock mode, an eighth carrier offset estimation
search range is added. Ranges from 0.10 to ~12.0 MHz
can be programmed with register CESR. QuickLock
mode locates frequency offsets when the 3dB
bandwidth of the channel falls within the offset search
range. When the search range is less than the channel
bandwidth, QuickLock search times further decrease.
When using QuickLock, set the Inband Power
Threshold, 2 dB Bandwidth Threshold, and 3 dB
Bandwidth Threshold registers to the QuickLock
recommended default values before initiating an
acquisition. Refer to Silicon Laboratories Application
Note “AN298: Si2107/08/09/10 Application
Programming Interface Example Software" for the
recommended default values. The recommended
values are documented in the Signal Acquisition section
of the application note.
When carrier offset estimation is complete, the CEL bit
is asserted. If an error is detected during carrier offset
estimation, the CEF bit is set. Carrier offset estimation
commences under the control of the acquisition
sequencer.
After the completion of a search, the estimated carrier
offset is stored in the carrier frequency error register,
CFER. If no signal is found, the CEF bit is asserted. The
value contained in CFER may be optionally transferred
to the CFO register to adjust the search center
frequency and permit the utilization of a smaller search
range for subsequent acquisitions. This relationship can
be expressed by the following equation:
Search center frequency
=
f_desired
+
CFO
×
---^f--^s---
2¹⁵
Hz
6.4.3. Carrier Recovery Loop
The carrier recovery loop is responsible for acquiring
frequency and phase lock to the incoming signal. When
lock is achieved, the carrier recovery lock indicator,
CRL, is asserted. If carrier recovery lock is not achieved
within a predefined timeout period, the device declares
carrier recovery failure by asserting the CRF bit. The
carrier recovery loop commences under the control of
the acquisition sequencer.
6.4.4. Symbol Timing Loop
The symbol timing recovery loop is responsible for
acquiring and tracking the symbol timing of the
incoming data signal. When lock is achieved, the
symbol timing loop lock indicator, STL, is asserted. If
symbol timing lock is not achieved within a predefined
timeout period, the device declares symbol timing loop
failure by asserting the STF bit. The symbol timing
recovery loop commences under the control of the
acquisition sequencer.
6.4.5. Automatic Fade Recovery
The device is designed to automatically recover lock in
the event of a fade condition. Fade recovery is
performed when any stage loses synchronization after
receiver lock has been achieved. It is assumed that
symbol rate, code rate, and puncturing pattern have not
changed; so, these parameters remain fixed during the
attempted reacquisition. The fade recovery sequence is
shown in Figure 15.
The fade recovery sequence continues until either
receiver lock is achieved or a new acquisition is
initiated.
Calibration
LO Tuning
Fail
Unlock
Unlock
Unlock
Unlock
Unlock
Analog AGC Search
Done
CFO Estimation
Done
Symbol Timing Loop
lock
Carrier Frequency Loop
lock
Viterbi Search
(Limited)
lock
Frame Search
lock
Receiver locked
Figure 15. Fade Recovery Sequence
Preliminary Rev. 0.81
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