SI4720-B20 Datasheet, PDF (25/48 Pages) Silicon Laboratories – BROADCAST FM RADIO TRANSCEIVER FOR PORTABLE APPLICATIONS

Si4720/21-B20
The transmit output (TXO) connects directly to the
transmit antenna with only one external inductor to
provide harmonic filtering. The output is programmable
over a 10 dB voltage range in 1 dB steps. The TXO
output pin can also be configured for loop antenna
support. Users are responsible for complying with local
regulations on RF transmission (FCC, ETSI, ARIB,
etc.).
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
including I²S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit
synchronization input clock (DCLK). The Si4720/21
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The Si4720/21 includes a low-noise stereo line input
(LIN/RIN) with programmable attenuation. To ensure
optimal audio performance, the Si4720/21 has a
transmit line input property that allows the user to
specify the peak amplitude of the analog input required
to reach maximum deviation level. The deviation levels
of the audio, pilot, and RDS/RBDS signals can be
independently programmed to customize FM transmitter
designs. The Si4720/21 has a programmable low audio
level and high audio level indicators that allows the user
to selectively enable and disable the carrier based on
the presence of audio content. In addition, the device
provides an overmodulation indicator to allow the user
to dynamically set the maximum deviation level. The
Si4720/21 has a programmable audio dynamic range
control that can be used to reduce the dynamic range of
the audio input signal and increase the volume at the
receiver. These features can dramatically improve the
end user’s listening experience.
The Si4720/21 is reset by applying a logic low on the
RST pin. This causes all register values to be reset to
their default values. The digital input/output interface
supply (V_IO) provides voltage to the RST, SEN, SDIO,
RCLK, DIN, DFS, and DCLK pins and can be connected
to the audio baseband processor's supply voltage to
save power and remove the need for voltage level
translators. RCLK is not required for register operation.
The Si4720/21 reference clock is programmable,
supporting many RCLK inputs as shown in Table 10.
The S4720/21 are part of a family of broadcast audio
solutions offered in standard, 3 x 3 mm 20-pin QFN
packages. All solutions are layout compatible, allowing
a single PCB to accommodate various feature offerings.
The Si4720/21 includes line inputs to the on-chip
analog-to-digital converters (ADC), a programmable
reference clock input, and a configurable digital audio
interface. The chip supports I²C-compliant 2-wire, 8-bit
SPI, and a 3-wire control interface.
5.2. Application Schematics and Operating
Modes
The application schematic for the Si4720/21 is shown in
Section "3. Typical Application Schematic" on page 20.
The Si4720/21 supports selectable analog, digital, or
concurrent analog and digital audio output modes. In
the analog output mode, pin 13 is ROUT, pin 14 is
LOUT, and pin 17 is GPO3. In the digital output mode,
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
Concurrent analog and digital audio output mode
requires pins 13, 14, 15, 16, and 17. In addition to
output mode, there is a clocking mode to clock the
Si4720/21 from a reference clock or crystal oscillator.
The user sets the operating modes with commands as
described in Section "6. Commands and Properties" on
page 36.
5.3. FM Receiver
The Si4720/21 FM receiver is based on the proven
Si4700/01/02/03 FM radio receiver. The part leverages
Silicon Laboratories' proven and patented Si4700/01 FM
broadcast radio receiver digital architecture, delivering
superior RF performance and interference rejection. The
proven digital techniques provide excellent sensitivity in
weak signal environments while providing superb
selectivity and inter-modulation immunity in strong signal
environments.
The FM receiver supports the worldwide FM broadcast
band (76 to 108 MHz) with channel spacings of 50–
200 kHz. The Low-IF architecture utilizes a single
converter stage and digitizes the signal using a high-
resolution analog-to-digital converter. The resulting
digital signals are further processed through an on-chip
DSP for digital channel selection, FM demodulation, and
ultimately stereo audio output. The audio output can be
directed either to an external headphone amplifier via
analog in/out or to other system ICs through digital audio
interface (I²S).
Rev. 1.0
25