SI4736-B20 Datasheet, PDF (22/38 Pages) Silicon Laboratories – BROADCAST WEATHER BAND RADIO RECEIVER

Si4736/37/38/39-B20
4.12. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated VCO.
The frequency synthesizer generates the quadrature local
oscillator signal used to downconvert the RF input to a low
intermediate frequency. The VCO frequency is locked to
the reference clock and adjusted with an AFC servo loop
during reception. The tuning frequency can be directly
programmed
using
the
WB_TUNE_FREQ,
FM_TUNE_FREQ, and AM_TUNE_FREQ commands.
The Si4736/37/38/39 supports channel spacing of 25 kHz
in WB mode; 50, 100, or 200 kHz in FM mode; and 9 or
10 kHz in AM mode.
4.13. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated using the FM_SEEK_START and
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Table 15).
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
Seek is not available for weather band.
4.14. Reference Clock
The Si4736/37/38/39 reference clock is programmable,
supporting RCLK frequencies in Table 12. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
voltage levels and Table 9, “FM Receiver
Characteristics” on page 12 for frequency tolerance
information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 16. This mode is enabled using the
POWER_UP command, see Table 14, “Si473x
Command Summary,” on page 25.
The Si4736/37/38/39 performance may be affected by
data activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4736/37/38/39 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4736/37/38/39 seek and tune operations. This
is achieved by keeping the bus quiet for all other
devices on the bus, and delaying tuner polling until the
tune or seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
4.15. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the
Si4736/37/38/39 and receive responses from the
device. The serial port can operate in three bus modes:
2-wire mode, 3-wire mode, or SPI mode. The
Si4736/37/38/39 selects the bus mode by sampling the
state of the GPO1 and GPO2 pins on the rising edge of
RST. The GPO1 pin includes an internal pull-up resistor,
which is connected while RST is low, and the GPO2 pin
includes an internal pull-down resistor, which is
connected while RST is low. Therefore, it is only
necessary for the user to actively drive pins which differ
from these states. See Table 13.
Table 13. Bus Mode Select on Rising Edge of
RST
Bus Mode
2-Wire
SPI
3-Wire
GPO1
1
1
0 (must drive)
GPO2
0
1 (must drive)
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
described in Section “4.16. GPO Outputs”. In any bus
mode, commands may only be sent after V_IO and V_DD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
4.15.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
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