SI4704-D50 Datasheet, PDF (22/34 Pages) Silicon Laboratories – BROADCAST FM RADIO RECEIVER FOR CONSUMER

Si4704/05-D50
4.13. Embedded Antenna Support
4.14. RDS Decoder (Si4705 Only)
The Si4704/05 is the first FM receiver to support the fast
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
Testing indicates that, when using Silicon Laboratories'
patented techniques, embedded antenna performance
can be very similar in many key metrics to a standard
half-wavelength antenna. Refer to “AN383: Si47XX
Antenna, Schematic, Layout, And Design Guidelines”
for additional details on the implementation of support
for an embedded antenna.
Figure 12 shows a conceptual block diagram of the
Si4704/05 architecture used to support the embedded
antenna. The half-wavelength FM receive antenna is
therefore optional. Host software can detect the
presence of an external antenna and switch between
the embedded antenna if desired.
Half-wavelength
antenna
FMI
Integrated
antenna
LPI
RFGND
LNA
AGC
Si4704/05
Figure 12. Conceptual Block Diagram of the
Si4704/05 Embedded Antenna Support
The Si4705 implements an RDS processor for symbol
decoding, block synchronization, error detection, and
error correction.
The Si4705 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
The Si4705 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
4.15. Reference Clock
The Si4704/05 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics” on page 5 for switching
voltage levels and Table 10, “Reference Clock and
Crystal Characteristics” on page 14 for frequency
tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 15. This mode is enabled using the
POWER_UP command. Refer to Refer to “AN332:
Si47xx Programming Guide”.
The Si4704/05 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4704/05 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4704/05 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
22
Rev. 1.0