SI3459 Datasheet, PDF (22/57 Pages) Silicon Laboratories – OCTAL IEEE 802.3AT POE PSE CONTROLLER

Si3459
Slave Address
tSCLA
Register Address
Write Data
START
0 1 A4 A3 A2 A1 A0* R/W#
ACK by IC
A7 A6 A5 A4 A3 A2 A1 A0
ACK by IC
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
Fixed IC
Address
Pin-Defined
Address
Write Sequence
*A0=0 for 1st Quad or A0=1 for 2nd Quad.
STOP by Master
Slave Address
Setup Register Address
tSCLA
Register Address
Slave Address
Transfer Data to Setup Address
tSCLA
Register Data
START
01
Fixed IC
Address
A4 A3 A2 A1 A0* R/W#
A7 A6 A5 A4 A3 A2 A1 A0
0 1 A4 A3 A2 A1 A0* R/W#
ACK by IC
ACK by IC
START
ACK by IC
Pin-Defined
Address
*A0=0 for 1st Quad or A0=1 for 2nd Quad.
Fixed IC
Address
Read Sequence
Pin-Defined
Address
Figure 11. I²C Read and Write Sequences
D7 D6 D5 D4 D3 D2 D1 D0
Not ACK by Master
STOP by Master
8-Bit Read
All registers can be accessed this way, but it is not recommended for reading registers storing parametric
measurement data (Iport and Vport, registers 0x19–0x1c, 0x29–0x2c, 0x39–0x3c, 0x49–0x4c).
Example Sequence
1. START condition, followed by the target slave's 7-bit address, and a write flag. The sequence is ACKed by
the Si3459.
2. Then an 8-bit Si3459 register address is provided followed by an ACK. These steps set up a pointer
register within the Si3459 that points to the address of an internal register to be read.
3. The transaction continues by sending a repeated START condition, followed by the target slave's 7-bit
address, and a read flag. This sequence is ACKed by the Si3459.
4. Then the 8-bit IC register data is provided by the Si3459 (slave). This occurrence is followed by a master
NACK (Not ACK).
5. Then the master frees the bus by sending a STOP condition.
See Figure 11, “I2C Read and Write Sequences,” on page 22 for more details.
8-Bit Write
All registers can be accessed this way (except the read only registers).
Example Sequence
1. START condition, followed by the Si3459 7-bit address, and a write flag. This is ACKed by the IC.
2. Then an 8-bit IC register address is provided followed by an ACK by the Si3459.
3. The transaction is completed by sending 8-bits of register data. This is ACKed by the Si3459.
4. Then the master frees the bus by sending a STOP condition.
See Figure 11, “I2C Read and Write Sequences,” on page 22 for more details.
16-Bit Read
This is the recommended access mode for reading registers storing parametric measurement data (Iport and
Vport, registers 0x19–0x1c, 0x29–0x2c, 0x39–0x3c, 0x49–0x4c). Only these registers can be accessed this way in
this mode.
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Rev. 1.1