AN332 Datasheet, PDF (211/302 Pages) Silicon Laboratories – Si47XX PROGRAMMING GUIDE

AN332
To send the TX_TUNE_FREQ command and arguments, the system controller sets SEN = 0. Next, the controller
drives the 9-bit control word on SDIO, consisting of the device address (A7:A5 = 101b), the write bit (0b), the
device address (A4 = 0), and the register address for the COMMAND2 register (A3:A0 = 0001b). The control word
is followed by a 16-bit data word, consisting of ARG2 followed by ARG3. The system controller then sets SEN = 1
and pulses the SCLK high and then low one final time. For commands requiring additional arguments, in the
COMMAND3 (ARG3, ARG4) and COMMAND4 (ARG5, ARG6) registers, the system controller would send these
next.
SEN
10
CTL
101000001b
ARG2
0x27
ARG3
0x7E
SEN
01
SCLK
Pulse
Next the system controller initiates the command by setting SEN = 0 and driving the 9-bit control word on SDIO,
consisting of the device address (A7:A5 = 101b), the write bit (0b), the device address (A4 = 0), and the register
address for the COMMAND1 register (A3:A0 = 0000b). The control word is followed by a 16-bit data word,
consisting of the CMD byte followed by ARG1 byte. The system controller then sets SEN = 1 and pulses the SCLK
high and then low one final time.
SEN
10
CTL
101000000b
CMD
0x30
ARG1
0x00
SEN
01
SCLK
Pulse
To read the status and response from the device, the system controller sets SEN = 0. Next, the controller drives the
9-bit control word 101101000b on SDIO, consisting of the device address (A7:A5 = 101b), the read bit (1b), the
device address (A4 = 0), and the register address for the STATUS/RESPONSE1 register (A3:A0 = 1000b). The
control word is followed by a 16-bit data word, consisting of STATUS followed by RESPONSE1. The system
controller then sets SEN = 1 and pulses the SCLK high and then low one final time. In this example, the STATUS
byte is 0x00, indicating that the CTS bit, bit 8, has not been set and that the response bytes are not ready for
reading and that the device is not ready to accept another command. RESP1 will be random until the CTS bit is
set. This process should be repeated until the STATUS byte indicates that CTS bit is set, 0x80 in this example.
SEN
10
CTL
101101000b
STATUS
0x00
RESP1
0x00
SEN
01
SCLK
Pulse
When the STATUS byte indicates that the CTS bit has been set, 0x80 in this example, the system controller may
read the RESPONSE bytes from the device in any order.
SEN
10
CTL
101101000b
STATUS
0x80
RESP1
0x00
SEN
01
SCLK
Pulse
Rev. 1.0
211