SI532 Datasheet, PDF (2/10 Pages) Silicon Laboratories – DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ)

Si532
1. Electrical Specifications
Table 1. Si532 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
LVDS/CML/LVPECL
CMOS
Specified at time of order by P/N.
10
—
945
MHz ^{Also available in bands from}
10
—
160
970 to 1134 MHz and 1213 to
1417 MHz.
Initial Accuracy
Temperature Stability
Aging
–1.5
—
1.5
ppm ^{Measured at +25 °C at time of ship-}
ping
–20
–50
—
—
+20
+50
Selectable option by P/N. See
ppm _{Section 4. "Ordering Information" on}
page 7.
—
—
±10
ppm ^{Frequency drift over projected 15 year}
life
Outputs
Symmetry
LVPECL: V_DD – 1.3 V (differential)
45
—
55
% _{LVDS: 1.25 V (differential)}
CMOS: V_DD/2
RMS Jitter for F_OUT > 500 MHz
F_OUT > 500 MHz
12 kHz to 20 MHz
—
0.27
—
ps Differential Modes:
50 kHz to 80 MHz
—
0.30
—
LVPECL/LVDS/CML
RMS Jitter for F_OUT of 125 to
500 MHz
125 < F_OUT < 500 MHz
Differential Modes:
12 kHz to 20 MHz
—
0.5
—
ps LVPECL/LVDS/CML
Period Jitter for F_OUT <160 MHz
Any output
Peak-to-Peak
—
5
—
ps N = 1000 cycles
RMS
—
1
—
LVPECL Output Option
mid-level
swing (diff)
V_DD – 1.42
1.1
—
—
V_DD – 1.25
1.9
V
V_PP
50 Ω to V_DD – 2.0 V
swing (single-ended)
0.50
—
0.93
V_PP
LVDS Output Option
mid-level
swing (diff)
1.125
0.32
1.2
0.40
1.275
0.50
V R_term = 100 Ω (differential)
V_PP
CML Output Option
mid-level
swing
—
V_DD – 0.75
—
0.70
0.95
1.20
V _{Rterm = 100 Ω (differential)}
V_PP
2
Preliminary Rev. 0.3