SI5318-EVB Datasheet, PDF (2/16 Pages) Silicon Laboratories – Differential inputs terminated on board

Si5318-EVB
1. Functional Overview
The Si5318-EVB is the customer evaluation board for
the Si5318 SONET/SDH Precision Port Card Clock IC.
It is supplied to customers for evaluation of the Si5318
device. The board provides access to signals
associated with normal operation of the device.
1.1. Power Consumption
Typical supply current draw for the Si5318-EVB is
140 mA.
1.2. Si5318 Control Inputs
The control inputs to the Si5318 are each routed from
the center pin of a SPDT switch, JP5, to the Si5318
device. Additionally, the switches at JP5 are connected
to GND on one side of the switch and to VDD33 on the
other side. This arrangement allows easy configuration
of each input to either a high or low state. To further
reduce the coupling of noise into the device through
these control inputs, the signals are routed on internal
layers between ground planes.
1.3. RSTN/CAL Settings for Normal Opera-
tion and Self-Calibration
The RSTN/CAL signal is an LVTTL input to the Si5318
and has an on-chip pulldown mechanism. This pin must
be set high for normal operation of the Si5318 device.
Setting RSTN/CAL low forces the Si5318 into the reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence.
The Si5318 device initiates self-calibration at powerup if
the RSTN/CAL signal is held high. A self-calibration of
the device also can be manually initiated by
momentarily pushing and then releasing the RSTN/CAL
switch, SW1.
Manually initiate self-calibration after changing the state
of the BWSEL[1:0].
Whether manually initiated or automatically initiated at
powerup, the self-calibration process requires a valid
input clock. If the self-calibration is initiated without a
valid clock present, the device waits for a valid clock
before completing the self-calibration. The Si5318 clock
output is set to the lower end of the operating frequency
range while the device waits for a valid clock. After the
clock input is validated, the calibration process runs to
completion, the device locks to the clock input, and the
clock output shifts to its target frequency. Subsequent
losses of the input clock signal do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.
1.4. Status Signals
The status outputs from the Si5318 device are each
routed to one pin of a two-row header. The signals are
arranged so that each signal has a ground pin adjacent
to the signal pin for reference. The row of signal pins is
marked with an “S”, and the row of ground pins is
marked with a “G”.
Visible indicators, D1 and D2, are added to the LOS and
CAL_ACTV signals. The LEDs glow when the signal is
active. The LOS LED D1 is illuminated when the device
does not recognize a valid clock input. The CAL_ACTV
LED, D2, is illuminated when the device is calibrating to
an input clock.
1.5. Differential Clock Input Signals
The differential clock inputs to the Si5318-EVB board
are ac coupled and terminated on the board at a
location near the SMA input connectors, J1 and J2. The
termination components are located on the top side of
the board resistors. The termination circuit consists of
two 50 Ω and a 0.1 µF capacitor, such that the positive
and negative inputs of the differential pair each see a
50 Ω termination to “ac ground,” and the line-to-line
termination impedance is 100 Ω.
For single-ended operation, supply a signal to one of
the differential inputs (usually the positive input). The
other input should be shorted to ground using an SMA
shorting plug. The on-board termination circuit provides
a 50 Ω termination to ac-ground for each leg of the
differential pair.
1.6. Differential Clock Output Signals
The differential clock outputs from the Si5318 device
are routed to the perimeter of the circuit board using
50 Ω transmission line structures. The capacitors that
provide ac-coupling are located near the clock output
SMA connectors, J4 and J5.
1.7. Internal Regulator Compensation
The Si5318-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0 Ω resistor. The
capacitor pads are populated with a low ESR 33 µF
tantalum capacitor. This is the suggested compensation
circuit for Si5318 devices.
The acceptable range for the time constant at this node
is 15 µs to 50 µs. The capacitor used on the board is a
33 µF capacitor with an ESR of .8 Ω. This yields a time
constant of 26.4 µs.
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Preliminary Rev. 1.0