SI50X-32X4-EVB Datasheet, PDF (2/8 Pages) Silicon Laboratories – This document describes the operation

Si50x-32x4-EVB
1. Functional Description
1.3. Preparing the EVB
The Si50x-32x4-EVB provides access to all I/O signals
for configuring, operating, and testing the device.
Jumpers and test points are provided as described
below.
1.1. Power Supply
The Si50x supports operation from nominal voltages of
1.8, 2.5, and 3.3 V. Supply VDD and GND are wired in
at the J1 ± terminals. Review the device data sheet and
part number for allowed configurations of output buffer
type and device power supply.
1.2. Jumpers
The jumpers at JP1 and JP2 allow one to pull up or pull
down OE or MODE to VDD or GND. (The MODE signal
is reserved for future use. It is not used by either the
Si500S or the Si500D.) The current silkscreen for these
jumpers is reproduced in Figure 1.
By default, the evaluation board is set up to support ac-
coupling of differential mode configured devices (i.e.,
Low Power LVPECL, LVDS, and SSTL). The stuffing
variations for the supported output modes are tabulated
in Table 1.
Table 1. Stuffing Variations
Driver
R1, R4 C2, C3
CMOS
empty empty
HCSL
Low Power
LVPECL
LVDS
LVPECL 2.5 V
empty
empty
empty
100 Ω
0.1 µF
0.1 µF
0.1 µF
0.1 µF
J2, J4
empty
filled
filled
Instrument
Termination
Active scope
probes^*
HI-Z
50 
filled
filled
50 
50 
LVPECL 3.3 V 200 Ω 0.1 µF
filled
50 
SSTL
empty 0.1 µF
filled
50 
*Note: Use of Coax and 50  termination produces good
signal integrity but incorrect signal levels and power;
use of Coax and Hi-Z produces extremely bad signal
integrity.
Figure 1. Jumpers Silkscreen
Pins 1 and 2 in Figure 1 refer respectively to the Si50x's
OE and MODE pins. The jumper positions are
illustrated in Figure 2.
The Si50x can be ordered with the OE pin pulled to the
desired state, so the JP1 jumper would typically be
needed only to access the opposing state.
JP1, Force OE high
1.3.1. LVPECL Biasing
Because the Si50x can support an LVPECL buffer type
(in addition to CMOS, HCSL, LVDS, or SSTL), pulldown
resistor locations (R1 and R4) are available for proper
output biasing. For LVPECL buffers, correct biasing can
be achieved through a variety of equivalent circuits; the
Si50x-32x4-EVB allows for a commonly used
approximation using pulldown resistors. After the output
biasing, the high-speed outputs are dc-blocked for
connection to differently biased inputs such as standard
test equipment.
1.4. Test Points
There are 4 through-hole test points as follows:
JP1, Force OE low
TP1—VDD
TP2—Output CLK_N
TP3—GND
JP2, Force Mode high
TP4—Output CLK
Test point TP1 is located near terminal J1. Test points
TP2–TP4 are located in between the output connectors.
JP2, Force Mode low
Figure 2. JP1–JP2 Jumper Positions
2
Rev. 0.2