SI3232PPT0-EVB Datasheet, PDF (2/18 Pages) Silicon Laboratories – EVALUATION BOARD FOR THE Si3232 DUAL PROSLIC

Si3232PPT0-EVB
ProSLIC LINC Evaluation Software
The ProSLIC LINC software is an executable program
that allows control and monitoring of the ProSLIC. It
utilizes the primary LPT port of a standard PC to
communicate to the ProSLIC’s SPI port.
To install the software, insert the Silicon Laboratories
ProSLIC CD into the computer. The setup routine can
be invoked by running the setup.exe program in the root
directory of the CD.
Invoking the ProSLIC LINC is achieved by double
clicking the ProSLIC LINC icon. Refer to the ProSLIC
LINC User Guide for software operation.
Si3232PPT0-EVB Dual ProSLIC Evaluation
Board Description
The schematics for the Dual ProSLIC evaluation
daughter card are shown in Figures 1 through 3. The
schematic in Figure 1 shows the Dual ProSLIC linecard
implementation. All circuitry pertaining to the telephony
function of the Dual ProSLIC is found here. Four-wire
analog is present on JP3 and JP4. Figure 2 contains a
number of options for secondary fault protection.
Secondary protection components can be selected for a
given level of protection against expected faults.
Figure 3 is the schematic that describes the serial
control interface, daisy chain ports, and power supply
filtering and connections. These schematics represent
typical linefeed components for the ProSLIC.
The layout of the Dual ProSLIC evaluation daughter
card is found in Figures 4–8. Figure 4 shows the
component placement while Figures 5 and 8 show the
two layers of component interconnect. Figures 6 and 7
show the inner ground and VDD planes. The signal flow
is four-wire analog on the left to two-wire analog on the
right.
Signal requirements for ProSLIC operation are PCLK
(PCM clock), FS (frame sync), and Serial IO. The
ProSLIC motherboard has a local oscillator with a
programmable logic device to provide the ProSLIC
PCLK and FS signals. The DIP switch (S2) sets the
PCLK frequency and controls the FS enable. See
Table 1 for S2 settings. JP3 and JP4 select this internal
clock source or an external PCM clock source. The
ProSLIC motherboard has been designed with digital
PCM interfaces (P2, P3, J8, and J11). These
connections are not used with the Si3232 Dual
ProSLIC. J9 and J10 allow access to the ProSLIC’s
clock inputs for connection to an actual telephone
system’s clocks. TIP and RING of the two-wire analog
interface is present at the RJ-11 connectors, J1 and J11
of the Dual ProSLIC daughter card.
The schematics of the ProSLIC motherboard are found
in Figures 9, 10, and 11. Figure 9 shows the
connections from the motherboard to the daughter card.
Figure 10 illustrates the LPT port connection to the SPI
drivers. The PCM highway and LED indicators are
shown in Figure 11.
The ProSLIC evaluation board is voltage programmable
with specific jumper settings. JP1 selects 3 V for
ProSLIC operation. JP2 selects 3 V or 5 V PCM source
level compatibility. These should be placed on the
expected setting.
Power is connected to the ProSLIC at J2, J3 and J4.
The 5 V is always required for the buffers, U2 and U3, to
interface to the parallel port. The ProSLIC can be
powered from 5 V or 3 V with the placement of a jumper
on JP1. The Protection Return connections on J6
should be connected to an appropriate ground for
TIP/RING fault testing. This return is tied to signal
ground on-board though it has a dedicated trace for
high current conditions. Serial control of the ProSLIC is
achieved by toggling select bits of a standard parallel
port. The parallel port connection is available at P1 and
J1.
Multiple dual ProSLIC cards can be daisy-chained by
stacking the cards. Stack up to eight cards by aligning
JS1–JS5 and pressing together. The ProSLIC LINC
Software allows channel selection for RAM and register
manipulation.
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Rev. 1.0