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C8051F351 Datasheet, PDF (2/2 Pages) Silicon Laboratories – 50 MIPS, 8 kB Flash, 24-Bit ADC, 28-Pin Mixed-Signal MCU
C8051F351
50 MIPS, 8 kB Flash, 24-Bit ADC, 28-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1x, MDCLK = 2.4567 MHz,
Decimation Ratio = 1920 unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
GLOBAL CHARACTERISTICS
Supply Voltage
2.7
3.6
Supply Current
Clock = 50 MHz
17
(CPU active)
Clock = 1 MHz
0.5
Clock = 32 kHz; VDD Monitor Enabled
16
Supply Current
Oscillator not running; VDD Monitor
0.1
(shutdown)
Disabled
Clock Frequency Range
DC
50
24-BIT A/D CONVERTER
Resolution
(no missing codes)
24
Integral Nonlinearity
Single-ended Mode
±15
Differential Mode
Offset Error
±5
Gain Error
±0.002
Common Mode Rejection
110
Ratio (CMRR)
Power Supply Rejection,
80
DC
Power Supply Current
230
8-BIT CURRENT-MODE D/A CONVERTERS
Resolution
Integral Nonlinearity
Differential Nonlinearity Guaranteed Monotonic
8
±0.5
±0.5
±1
UNITS
V
mA
mA
µA
µA
MHz
bits
ppm FS
ppm
%
dB
dB
µA
bits
LSB
LSB
Package Information
Bottom View
L
7
6
D2
5
D2
2
4
3
2
1
DETAIL 1
15
16
17
18
R
19
20
21
6xe
D
Side View
MM
MIN TYP MAX
A 0.80 0.90 1.00
A1 0 0.02 0.05
A2 0 0.65 1.00
A3
0.25
b 0.18 0.23 0.30
D
5.00
D2 2.90 3.15 3.35
E
5.00
E2 2.90 3.15 3.35
e
0.5
L 0.45 0.55 0.65
N
28
ND
7
NE
7
R 0.09
AA
0.435
BB
0.435
CC
0.18
DD
0.18
DETAIL 1
AA
C8051F350DK Development Kit
e
CC
Precision Mixed Signal
Copyright © 2005 by Silicon Laboratories
5.5.2005
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