C8051F320 Datasheet, PDF (2/2 Pages) Silicon Laboratories – On-chip debug circuity gacilitates full speed, non-intrusive in-system debug (no emulator required)

C8051F320
USB, 25 MIPS, 16 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T_A = 0 to +70 C°, VREG = 5.0 V unless otherwise specified)
Parameter
Global Characteristics
Conditions
Min Typ Max Units
Regulator Input Voltage (REGIN)
V_DD (VREG Output)
V_REG Bias Current
Supply Current with
CPU and USB active
Supply Current (suspend mode, Oscillator off)
CPU System Clock Range
Internal Oscillator & Clocks
V_REG Enabled
CPU Clock = 24 MHz,
USB Clock = 48 MHz
CPU Clock = 12 MHz,
USB Clock = 6 MHz
V_DD Monitor Enabled; V_REG Disabled
V_DD Monitor Disabled; V_REG Disabled
4.0
—
5.25
3.0
3.3
3.6
—
70
—
18
—
—
9
—
30
<0.1
—
DC
—
25
V
V
µA
mA
mA
µA
µA
MHz
Frequency
USB Clock
A/D Converter
Clock Recovery Enabled
Clock Recovery Disabled
Full-Speed Operation
Low-Speed Operation
11.97
11.82
47.88
5.91
12.0
12.0
48.0
6.0
12.03
12.18
48.12
6.09
MHz
MHz
MHz
MHz
Resolution
Integral Nonlinearity
Differential Nonlinearity
Signal-to-Noise Plus Distortion
Throughput Rate
Input Voltage Range
Comparator
Response Time Mode0
Current Consumption Mode0
Response Time Mode1
Current Consumption Mode1
Response Time Mode2
Current Consumption Mode2
Response Time Mode3
Current Consumption Mode3
Guaranteed Monotonic
(CP+) – (CP-) = 100 mV
(CP+) – (CP-) = 100 mV
(CP+) – (CP-) = 100 mV
(CP+) – (CP-) = 100 mV
10
bits
—
±½
±1
LSB
—
±½
±1
LSB
53
—
—
dB
—
—
200
ksps
0
—
V_REF
V
—
0.1
—
µs
—
7.6
—
µA
—
0.18
—
µs
—
3.2
—
µA
—
0.32
—
µs
—
1.3
—
µA
—
1
—
µs
—
0.4
—
µA
Package Information
C8051F320DK Development Kit
D
D1
32
PIN 1
IDENTIFIER ₁
A2
b
E1 _E
A
A1
e
MIN NOM MAX
(mm) (mm) (mm)
A - - 1.60
A1 0.05 - 0.15
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
D - 9.00 -
D1 - 7.00 -
e - 0.80 -
E - 9.00 -
E1 - 7.00 -
USB
Copyright © 2006 by Silicon Laboratories
1.9.2006
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