AN843 Datasheet, PDF (2/4 Pages) Silicon Laboratories – Using Analog Components to Manage Power in Low-Power Solar Systems

AN843
Figure 2. An Ultra-Low-Power Op Amp Offers Simple, Positive Polarity Output to Support a Zero
Bias Condition
For a more comprehensive assessment, the circuit in Fig. 3 tests the solar source to see if it can handle the load.
The circuit shown makes this assessment without burdening the microcontroller and risking collapse of the supply
during measurement.
Figure 3. An Ultra-Low-Power Op-Amp-based Circuit Assesses A Pv Solar-Cell Source
Approximately once per 100 ms, the circuit disconnects the solar-cell power source from its reservoir capacitor and
load, applying a test load (R1) and assessing the resulting voltage drop. If the voltage drops 25% or more, the
result is latched into U2 and the power status is provided to the microcontroller.
This ultra-low power circuit draws less than 3 µA at 1 V. Op amp U1 provides the timer function and controls
transistor switches T1 and T2 to apply the test load while simultaneously disconnecting the load. Capacitor C1
temporarily holds the voltage to keep this circuitry and any standby loads powered. Op amp U2 serves as a
comparator, tripping when the power source drops more than 25% (with 5% hysteresis). Transistor T3 latches the
result, while transistor T4 resets the latch during each assessment period to ensure a fresh reading.
Such test loading is useful for determining the available power from a solar cell, since merely measuring the open
circuit voltage generally does not provide an accurate assessment.
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Rev. 1.0