1409081 Datasheet, PDF (2/5 Pages) Silicon Laboratories – This note already existed in the data sheet in the Reset Sources chapter, and it’s been added to additional locations to make it more prominent.

Bulletin #1409081
_____________________________________________________________________________________________________
Use VDD Monitor high setting only when writing Flash
– Updated step 4 in “VDD Maintenance and the VDD monitor” on page 130 to mention using the VDD
monitor in the high setting during flash write/erase operations.
This step previously mentioned using the VDD monitor, but did not specify that the VDD monitor must
be in the high setting in order to write to flash.
Note: When programming the Flash in-system, the VDD Monitor must be set to the high threshold
setting. For the highest system reliability, the time the VDD Monitor is set to the high threshold setting
should be
minimized (e.g., setting the VDD Monitor to the high threshold setting just before the Flash write
operation
and then changing it back to the low threshold setting immediately after the Flash write operation).
Set ZTCEN before entering oscillator suspend
– Updated the SUSPEND bit description in OSCICN (SFR Definition 18.2) to mention that firmware must
set the ZTCEN bit in REF0CN (SFR Definition 7.1) before entering suspend.
This information was already present as a note in section 15.3 Suspend Mode, and it’s been added to
the bit description to make it more prominent.
ZTCEN Zero Temperature Coefficient Bias Enable
Bit.
This bit must be set to 1b before entering
oscillator suspend mode.
IFRDY flag does not accurately reflect the state of the oscillator
– Added a note to the IFRDY flag in the OSCICN register (SFR Definition 18.2) that the flag may not
accurately reflect the state of the oscillator.
IFRDY Internal Oscillator Frequency Ready Flag.
Note: This flag may not accurately reflect the state of the oscillator. Firmware should not use this
flag to determine if the oscillator is running.
VREGIN ramp time max 1 ms for power on specification
– Added VREGIN Ramp Time max 1 ms for Power On spec to Table 5.4, “Reset Electrical
Characteristics,” on page 41.
– Updated “VDD Maintenance and the VDD monitor” on page 130 to refer to 1 ms VREGIN ramp time
instead of 1 ms VDD ramp time.
This specification was previously mentioned in the Flash Write and Erase Guidelines section. It is now
added to the electrical specifications to make it more prominent.
Limited cold programming temperature range for industrial grade (-I) devices
W7206F2 Silicon Labs Bulletin rev I
The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in
part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 4