SI3460 Datasheet, PDF (15/22 Pages) Silicon Laboratories – IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER

Si3460
7. Si3460 Pin Descriptions
Si3460 pin functionality is described in Table 10. Note that the information applies to the Si3460 device pins, while
the Si3460-EVB User’s Guide describes the inputs and outputs of the evaluation system.
The electrical characteristics of the Si3460-EVB are summarized in Table 1, “Si3460-EVB Performance
Characteristics Summary,” on page 4. Refer to the complete Si3460-EVB schematics and BOM listing for
information about the external components needed for the complete PSE and dc-dc controller application circuit.
GATE ¹
CTRL1 ²
VDD 3
CTRL2 4
250KHZ 5
GND
10 _STATUS
9 ISENSE
8 _RST
7 _VSENSE
6 DETA
Pin # Pin Name
1
GATE
2
CTRL1
3
VDD
4
CTRL2
5 250KHZ
6
DETA
7 VSENSE
Table 10. Si3460 Pin Functionality
Pin Type
Digital output
Digital output
Power
Digital output
Digital output
Analog input
Analog input
Pin Function
A logic low on this pin turns on the output FET to enable the PSE
output voltage. Refer to the Si3460-EVB schematics for the circuit
connections between the external FET and this pin.
The output of this pin is averaged with CTRL2 to control PWM duty
cycle for the dc-dc controller. This output also controls the dc output
for the detection circuitry.
3.3 V power supply input.
The output of this pin is averaged with CTRL1 to control PWM duty
cycle for the dc-dc controller. This output also controls the dc output
for the detection circuitry.
This is a 250 kHz square wave (50% duty cycle) that is filtered into
a triangular wave signal for the dc-dc controller. The 250 kHz out-
put on this pin is gated off when it is desired to keep the switcher
FET off.
DETA is an analog input pin. During the detection process, the
CTRL1 and CTRL2 pin duty cycle is varied to generate filtered dc
voltages across a resistive bridge. The null indicator for this bridge
is connected to pin DETA.
VSENSE is an analog input used for sensing the PSE output volt-
age.
Preliminary Rev. 0.4
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