SI4010-C2 Datasheet, PDF (124/156 Pages) Silicon Laboratories – CRYSTAL-LESS SOC RF TRANSMITTER

Si4010-C2
31.1. Register Description
SFR Definition 31.1. CLKOUT_SET
Bit
7
6
5
4
3
2
1
0
Name ^{CLKOUT_ CLKOUT_ CLKOUT_}
CLR
INV
SYM
CLKOUT_DIV[4:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x8F
Bit Name
Function
CLKOUT Clear.
Write 1 to this bit clears the generated clock divider. The generated clock output is
forced to 0.
Reading this bit has CLKOUT_IDLE meaning. If read as 1 then it indicates that the
clock divider generator is idle. It can be used to wait for the clock to get idle after the
7
CLKOUT_
CLR
user clock output was disabled by PORT_SET.PORT_CLKEN=0. If this bit is read as
0 the clock division generator by factor 2 and above is running and the current user
clock period is still in progress.
The user could use this bit to synchronously switch the CLKOUT_DIV division factor,
but it is not necessary. The synchronous clock period switching is built in the hard-
ware. See the CLKOUT_DIV field description of this register. To switch the clocks
immediately without waiting for the current period to end, write 1 to this bit. The write
1 to this bit can be combined with setting the new CLKOUT_DIV value in this register
at the same time.
CLKOUT Inversion.
Invert the generated clock. The inverter is at the very end of the clock generation
CLKOUT_ _{chain. Normally, if this bit is 0, if the generated clock is disabled the output is at 0.}
6
INV
With this bit set to 1 the output is inverted, therefore the generated clock stops at 1.
This bit must be set before customer clock is enabled to the port output by setting
PORT_SET.PORT_CLKEN=1. If changed later the clock inversion takes effect imme-
diately with possibility of short clock pulse being generated at the clock output.
124
Rev. 1.0