EM357-RTR Datasheet, PDF (116/241 Pages) Silicon Laboratories – High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

9.2. GPIO Usage
The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs. As with all EM35x digital
inputs, a GPIO used as a timer input can be shared with other uses of the same pin. Available timer inputs include
an external timer clock, a clock mask, and four input channels. Any GPIO used as a timer output must be
configured as an alternate output and is controlled only by the timer.
Many of the GPIOs that can be assigned as timer outputs can also be used by another on-chip peripheral such as
a serial controller. Using a GPIO as a timer output takes precedence over another peripheral function, as long as
the channel is configured as an output in the TIMx_CCMR1 register and is enabled in the TIMx_CCER register.
The GPIOs that can be used by Timer 1 are fixed, but the GPIOs that can be used as Timer 2 channels can be
mapped to either of two pins, as shown in Table 9.1. The Timer 2 Option Register (TIM2_OR) has four single bit
fields (TIM_REMAPCy) that control whether a Timer 2 channel is mapped to its default GPIO in port PA, or
remapped to a GPIO in PB.
Table 9.1 specifies the pins that may be assigned to Timer 1 and Timer 2 functions.
Table 9.1. Timer GPIO Usage
Signal
(Direction)
Timer 1
Timer 2
(TIM_REMAPCy = 0)
Timer 2
(TIM_REMAPCy = 1)
TIMxC1
(In or Out)
PB6
PA0
PB1
TIMxC2
(In or Out)
PB7
PA3
PB2
TIMxC3
(In or Out)
PA6
PA1
PB3
TIMxC4
(In or Out)
PA7
PA2
PB4
TIMxCLK
(In)
PB0
PB5
PB5
TIMxMSK
(In)
PB5
PB0
PB0
The TIMxCLK and TIMxMSK inputs can be used only in the external clock modes; refer to "9.3.3.2. External Clock
Source Mode 1" on page 123 and "9.3.3.3. External Clock Source Mode 2" on page 124 for details concerning their
use.
9.3. Timer Functional Description
9.3.1. Time-Base Unit
The main block of the general purpose timer is a 16-bit counter with its related auto-reload register. The counter
can count up, down, or alternate up and down. The counter clock can be divided by a prescaler.
The counter, the auto-reload register, and the prescaler register can be written to or read by software. This is true
even when the counter is running.
The time-base unit includes:
Counter Register (TIMx_CNT)
Prescaler Register (TIMx_PSC)
Auto-Reload Register (TIMx_ARR)
Some timer registers cannot be directly accessed by software, which instead reads and writes a “buffer register”.
The internal registers actually used for timer operations are called “shadow registers”.
The auto-reload register is buffered. Writing to or reading from the auto-reload register accesses the buffer register.
The contents of the buffer register are transferred into the shadow register permanently or at each update event
(UEV), depending on the auto-reload buffer enable bit (TIM_ARBE) in the TIMx_CR1 register. The UEV is
generated when both the counter reaches the overflow (or underflow when down-counting) and when the
TIM_UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. UEV generation is
described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit
(TIM_CEN) in the TIMx_CR1 register is set. Refer also to the slave mode controller description in "9.3.13. Timers
Rev 1.3
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