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EFM32TG108 Datasheet, PDF (11/48 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode
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3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol
tEM10
Parameter
Transition time from EM1 to EM0
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
Min
Typ
Max
Unit
0
HF-
CORE-
CLK
cycles
2
µs
2
µs
163
µs
3.6 Power Management
The EFM32TG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.5. Power Management
Symbol
VBODextthr-
VBODextthr+
VPORthr+
tRESET
CDECOUPLE
Parameter
Condition
Min
Typ
BOD threshold on
1.74
falling external sup-
ply voltage
BOD threshold on
rising external sup-
ply voltage
Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
Max
Unit
1.96 V
1.85
1.98 V
1.98 V
163
µs
1
µF
2015-03-06 - EFM32TG108FXX - d0032_Rev1.40
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