SI3220 Datasheet, PDF (10/112 Pages) Silicon Laboratories – DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC

Si3220/25
Table 5. AC Characteristics
(V_DD, V_DD1 – V_DD4 = 3.13 to 5.25 V, T_A = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max Unit
TX/RX Performance
Overload Level
2.5
—
Overload Compression
2-Wire – PCM
Figure 6
—
Single Frequency Distortion¹
2-Wire – PCM or PCM – 2-Wire:
—
–85
200 Hz to 3.4 kHz
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
—
–87
Signal-to-(Noise + Distortion)
Ratio²
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Figure 5
—
Active off-hook, and OHT, any Z_T
Audio Tone Generator Signal-to-
0 dBm0, Active off-hook, and
46
—
Distortion Ratio²
OHT, any Z_T
Intermodulation Distortion
—
—
Gain Accuracy²
2-Wire to PCM or PCM to 2-Wire –0.25
—
1014 Hz, Any gain setting
Attenuation Distortion vs. Freq.
0 dBm 0
Figure 7,8 —
—
V_PK
—
–65
dB
–65
dB
—
—
dB
–41
dB
+0.25 dB
—
—
Group Delay vs. Frequency
Gain Tracking³
1014 Hz sine wave,
reference level –10 dBm
Signal level:
3 dB to –37 dB
–37 dB to –50 dB
Figure 9
—
—
—
—
—
—
—
—
—
± 0.25 dB
—
—
± 0.5
dB
–50 dB to –60 dB
—
—
± 1.0
dB
Round-Trip Group Delay
1014 Hz, Within same time-slot
—
600
700
µs
Crosstalk between Channels
0 dBm0,
TX or RX to TX
300 Hz to 3.4 kHz
—
–108
–75
dB
TX or RX to RX
300 Hz to 3.4 kHz
—
–108
–75
dB
Gain Step Increment⁴
Step size around 0 dB
—
±0.0005 —
dB
2-Wire Return Loss⁵
200 Hz to 3.4 kHz
26
30
—
dB
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as V_TIP – V_RING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See "3.25. Audio Path Processing" on page 69.
5. V_DD1 – V_DD4 = 3.3 V, V_BAT = –52 V, no fuse resistors, R_L = 600 Ω, Z_S = 600 Ω synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
10
Rev. 1.2