CP2112-EK Datasheet, PDF (10/14 Pages) Silicon Laboratories – Quick Start Guide

CP2112-EK
7. Target Board
The CP2112 Evaluation Kit includes an evaluation board with a CP2112 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the evaluation board. Refer to Figure 9 for the locations of the various I/O connectors. Refer to Figure 10,
“CP2112 Evaluation Board Schematic” for information regarding the SMBus pull-up resistors that are located on
the target board.
P1
USB connector for USB interface
H1
Access Connector for SMBus interface (SDA, SCL, GND, Pull-Up Voltage)
J1, J2, J3, J4
GPIO access connectors
J6
Power connector
J7
SMBus pull-up voltage connector
J8
Red SUSPEND LED connector
DS0–DS7
Green GPIO LEDs
DS8
Red SUSPEND LED
TB1
SMBus interface terminal block
J4
J8
TB1
SILICON LABS
GND
H1
SDA
SCL
GND
EXT_PU
DS7
DS6
J3
DS5
DS4
J2
DS3
SUSPEND
DS8
P1
U1
CP2112
EXT_PU
DS2
J1
CP2112-EK
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DS1
DS0
J7
SMBUS PU_V
J6
Figure 9. CP2112 Evaluation Board with Default Shorting Blocks Installed
7.1. LED Headers (J1, J2, J3, J4)
Connectors J1, J2, J3, and J4 are provided to allow access to the GPIO pins on the CP2112. Place shorting blocks
on J1, J2, J3, and J4 to connect the GPIO pins to the eight green LEDs, DS0–DS7. These LEDs can be used to
indicate active communications through the CP2112. Table 1 lists the LED corresponding to each header position.
Table 1. J2 and J3 LED Locations
LED
DS0
DS1
DS2
DS3
DS4
DS5
DS6
DS7
Pins
J1[3:4]
J1[1:2]
J2[3:4]
J2[1:2]
J3[3:4]
J3[1:2]
J4[3:4]
J4[1:2]
10
Rev. 0.3