SI5023-EVB Datasheet, PDF (1/12 Pages) Silicon Laboratories – Simple jumper configuration

Si5023-EVB
EVALUATION BOARD FOR Si5023 SiPHY™ MULTI-RATE
SONET/SDH CLOCK AND DATA RECOVERY IC
Description
Features
The Si5023 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5023
SiPHY™ multi-rate SONET/SDH clock and data
recovery IC. The Si5023 CDR supports OC-48/12/3,
STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates.
All high-speed I/Os are ac coupled to ease interfacing to
industry standard test equipment.
! Single 3.3 V power supply
! Differential I/Os ac coupled
! Simple jumper configuration
Functional Block Diagram
Pulse
Generator
Pattern
Generator
VDD
210 Ω
Z_C = 50 Ω
Z_C = 50 Ω
348 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
J^Zu^Cm⁼p⁵e⁰rs^Ω
Z_C = 50 Ω
+
REFCLK
–
+
CLKOUT
–
Si5023
+
DATAIN
–
+
DATAOUT
–
RATESEL0
LOS
+RATESEL1
RLTERFCLK
LOL+
CLKOUT
–DSQLCH BER_ALM–
RESET/CAL
CLKDSB^SLⁱ⁵⁰²³
+
DATAIN
–
+
BDEART_AMOOUNT
–
LROAST_ELSVELL0
RATESEL1
SLTLIRCE_LVL
DSQLCH
LOS
RELOXTL
BER_ALM
RESET/CAL
BER_LVL
CLKDSBL
Si5023-EVB Rev B
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Test Points
Z_C = 50 Ω
Z_C = 50 Ω
5k
Jitter
Analyzer
Scope
Pattern
Analyzer
10 kΩ
Test Points
Rev. 1.1 1/04
Copyright © 2004 by Silicon Laboratories
Si5023-EVB-11