SI5017-EVB Datasheet, PDF (1/12 Pages) Silicon Laboratories – Simple jumper configuration

Si5017-EVB
EVALUATION BOARD FOR Si5017 SiPHY™ SONET/SDH
CLOCK AND DATA RECOVERY IC
Description
Features
The Si5017 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5017
SiPHY™ SONET/SDH clock and data recovery IC. The
Si5017 CDR supports OC-48, STM-16, and 2.7 Gbps
FEC rates.
All high-speed I/Os are ac coupled to ease interfacing to
industry standard test equipment.
„ Single 3.3 V power supply
„ Differential I/Os ac coupled
„ Simple jumper configuration
Functional Block Diagram
Pulse
Generator
Pattern
Generator
VDD
210 Ω
Z_C = 50 Ω
Z_C = 50 Ω
348Ω
Z_C = 50 Ω
Z_C = 50 Ω
Jumpers
+
REFCLK
–
+
CLKOUT
–
Si5017
+
DATAIN
–
+
DATAOUT
–
LOS
LTR
DSQLCH
LOL
BER_ALM
RESET/CAL
CLKDSBL
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Z_C = 50 Ω
Jitter
Analyzer
Scope
Pattern
Analyzer
Test Points
LOS_LVL
SLICE_LVL
REXT
BER_LVL
Si5017-EVB
10 kΩ
Rev. 1.0 12/02
Copyright © 2002 by Silicon Laboratories
Si5017-EVB-DS10