SI5010-EVB Datasheet, PDF (1/11 Pages) Silicon Laboratories – Simple jumper configuration

Si5010-EVB
EVALUATION BOARD FOR Si5010 OC-12/3, STM-4/1
SONET/SDH CLOCK AND DATA RECOVERY IC
Description
Features
The Si5010 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5010
multi-rate OC-12/3 and STM-4/1 clock and data
recovery (CDR) device.
All high-speed I/Os are ac coupled to ease interfacing to
industry standard test equipment
 Single 2.5 V power supply
 Differential I/Os ac coupled
 Simple jumper configuration
Function Block Diagram
Pulse
Generator
Pattern
Generator
Z_C = 50 
Z_C = 50 
Z_C = 50 
Z_C = 50 
+
REFCLK
–
+
CLKOUT
–
Si5010
+
DATAIN
–
+
DATAOUT
–
RATESEL
PW RDN/CAL
LOL
REXT
Ju m p ers
Si5010-EVB
Rev C
Z_C = 50 
Z_C = 50 
Z_C = 50 
Z_C = 50 
Jitter
Analyzer
Scope
Pattern
Analyzer
10 k
Test
Point
Rev. 1.0 12/02
Copyright © 2016 by Silicon Laboratories
Si5010-EVB-10