SI2704-A10 Datasheet, PDF (1/46 Pages) Silicon Laboratories – EMI MITIGATING 2.1X 5 W CLASS D AUDIO AMPLIFIER

Si2704/05/06/07-A10
EMI MITIGATING 2.1X 5 W CLASS D AUDIO AMPLIFIER
Features
 Digital input Delta-Sigma PWM
 Programmable 7 band parametric EQ,
 Patent-pending EMI mitigation
dynamic range compressor, tone control
 AM radio band noise-free notch
 Crossbar input mixer with scaling
 GSM/iPhone friendly
 Digital tone and alert generation
 Wideband PWM carrier spreading
 128 dB volume control in 0.5 dB steps
 Power stage slew rate control
 Multiple low power operating modes
 Power stage feedback for PSR/THD  Over-current and over-temperature
 2x 5 W @ 3  BTL; 2x 3 W @ 8  BTL detection w/ auto recovery
 88% efficiency with >50 dB PSRR
 Pop and click free operation
 95 dB dynamic range and <0.1% THD  Standard 2-wire control w/ 2 addresses
 Stereo PWM DAC line analog outputs  System flexibility w/ 3 multi-function pins
 Master/slave I²S w/ 3 inputs & 1 output ^{ Dual supply voltage: 2.7–3.6 V main}
 Automatic digital audio rate detection
and 4.0–6.6 V power stage
 Standard audio rates from 32–192 kHz ^{ Available in 4x4 24-pin Power QFN and}
 Audio activity detector w/ auto-standby
7x7 48-pin Power eTQFP package
 Operates from external XTAL or clock
Both Pb-free/RoHS compliant
 Buffered master/regulator clock output
Applications
 PMP/MP3 docking stations
 Portable consumer audio electronics
 Table top and portable radios
Description
 Active/wireless speakers
 TVs and monitors
 TV sound bars
The Si2704/05/06/07 EMI mitigating 2.1 digital audio processing Class D
amplifier integrates a power stage, PWM DAC, and digital audio processing
(DAP) for simplified, low cost, power efficient system designs in consumer
audio electronics. The digital input amplifier features delta-sigma PWM and
innovative EMI mitigation technology for producing high-quality audio while
effectively managing PWM switching noise for enhanced EMI compliance and
AM/FM radio co-existence, while also being GSM/iPhone friendly.
Functional Block Diagram
2.7 – 3.6 V VDD
Supply
CLKO
I²S
1.62 – 3.6 V
VIO
Supply
MFP
2-Wire Control
Si270x Digital Class-D Amplifier
LDO
Clock
Generation
DSP
I²S/AAD
Mixer
ASRC
Tone Gen.
Cross-over Filter
Volume Control
Tone Control
7-Band EQ
DRC
MFP Control
CH 1
PWM
Power
Stage
Feedback
PWM ^{CH 2}
Power
Stage
System Control
Over Current
Over Temp
PWM DAC
LF
4.0 – 6.6 V
VPP
Supply
RF
AUXOL/R
Ordering Information:
See page 37.
Pin Assignments
Si2704/05/06/07
24 23 22 21 20 19
DCLK 1
DIN 2
VIO 3
SCLK 4
SDIO 5
CLKO 6
GND PAD
(Back Paddle)
Top Down View
24-Pin QFN Package
18 OUTPL
17 OUTNL
16 GNDL
15 GNDR
14 OUTNR
13 OUTPR
7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
DFS 2
DCLK 3
DIN 4
VIO 5
GND 6
SCLK 7
SDIO 8
CLKO 9
NC 10
NC 11
NC 12
GND PAD
(Back Paddle)
Top Down View
48-Pin eTQFP Package
36 NC
35 VPPL
34 OUTPL
33 GND
32 OUTNL
31 GNDL
30 GNDR
29 OUTNR
28 GND
27 OUTPR
26 VPPR
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
Rev. 0.6 8/10
Copyright © 2010 by Silicon Laboratories
Si2704/05/06/07-A10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.