CP2130 Datasheet, PDF (1/27 Pages) Silicon Laboratories – SINGLE-CHIP USB-TO-SPI BRIDGE

CP2130
SINGLE-CHIP USB-TO-SPI BRIDGE
Single-Chip USB-to-SPI Bridge
Integrated clock; no external crystal required
Integrated USB transceiver; no external resistors
required
Integrated 348 Byte one-time programmable ROM for
product customization
On-chip power-on reset circuit
On-chip voltage regulator: 3.45 V output
Uses USB Bulk Mode transactions for high throughput
- Configurable priority for reads and writes
USB Peripheral Function Controller
USB Specification 2.0 compliant; full-speed (12 Mbps)
USB suspend states supported and indicated via
suspend output pins
USB Interface
Windows 8^®, 7^®, Vista^®, and XP^®
Open access to interface specification
Windows Libraries
APIs for quick application development
Supports Windows 8^®, 7^®, Vista^®, and XP^® (SP2 &
SP3)
Packages
RoHS-compliant 24-QFN package (4x4 mm)
SPI Controller
3 or 4-wire master mode operation
Configurable clock rate
- 12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz,
187.5 kHz, 93.75 kHz
Clock phase and polarity control
Chip select mode and toggle
Programmable SPI delay (post-assert, inter-byte, pre-
deassert)
11 Configurable GPIO Pins with Alternate Functions
Usable as inputs, open-drain outputs, or push-pull
outputs
Up to 11 chip select outputs
Ready-to-read pin allows for external signal to trigger
SPI read operations
Ability to count edges or pulses using the Event Counter
Up to 11 USB remote wakeup sources
SPI activity indication (toggles to indicate SPI activity)
Configurable clock output (93.75 kHz to 24 MHz)
Supply Voltage
Self powered (regulator disabled): 3.0 to 3.6 V
Self powered (regulator enabled): 3.0 to 5.25 V
USB bus powered: 4.0 to 5.25 V
I/O voltage: 1.8 V to V_DD
Ordering Part Numbers
CP2130-F01-GM
Temperature Range: –40 to +85 °C
CP2130
Connect to VBUS
or External Supply
USB
Connector
VBUS
D+
D-
GND
Hardware Reset
Logic Level
Supply
(1.8 V to VDD)
VREGIN
VDD
Voltage
48 MHz
Regulator Oscillator
GND
USB Interface
VBUS
D+
Full-Speed Peripheral
D-
12 Mbps
Function
Transceiver Controller
RESET
VPP
348 Byte PROM
(Product Customization)
VIO
I/O Power and Logic Levels
SPI Controller
MISO
MOSI
SCK
Multi-Function
Signals
GPIO
SPI Chip Select
SPI ReadyToRead
SPI Event Counter
Clock Output
SPI Activity
USB Suspend
Remote Wakeup
GPIO.0_CS0
GPIO.1_CS1
GPIO.2_CS2
GPIO.3_CS3_RTR
GPIO.4_CS4_EVTCNTR
GPIO.5_CS5_CLKOUT
GPIO.6_CS6
GPIO.7_CS7
GPIO.8_CS8_SPIACT
GPIO.9_CS9_SUSPEND
GPIO.10_CS10_SUSPEND
To SPI
Slave
Devices
Multi-
Function
Signals to
External
Circuitry
Figure 1. Example System Diagram
Rev. 0.7 1/14
Copyright © 2014 by Silicon Laboratories
CP2130
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.