CP2112 Datasheet, PDF (1/22 Pages) Silicon Laboratories – SINGLE-CHIP HID USB TO SMBUS MASTER BRIDGE

CP2112
SINGLE-CHIP HID USB TO SMBUS MASTER BRIDGE
Single-Chip HID USB to SMBus Master Bridge
Integrated USB transceiver; no external resistors or
crystal required
SMBus master device
GPIO can be configured as Input/Output and Open-
Drain/Push-Pull
512 Byte SMBus data buffer
Integrated 194 Byte One-Time Programmable ROM for
storing customizable product information
On-chip power-on reset circuit
On-chip voltage regulator: 3.45 V output
USB Peripheral Function Controller
USB Specification 2.0 compliant; full-speed (12 Mbps)
USB Suspend states supported via SUSPEND and
SUSPEND pins
HID Interface
Standard USB class device requires no custom driver
Windows 7, Vista, XP, Server 2003, 2000
Win CE 6.0, 5.0, and 4.2
Mac OS X
Linux
Open access to interface specification
Windows and Mac HID-to-SMBus Libraries
APIs for quick application development
Supports Windows 7, Vista, XP, Server 2003, 2000
Supports Mac OS X
SMBus Configuration Options
Configurable Clock Speed
Device Address: 7-bit value that is the slave address of
the CP2112. The device will only ACK this address, but
will not respond to any read/write requests
Read/Write Timeouts
SCL Low Timeout
Retry Counter Timeout
GPIO Interface Features
8 GPIO pins with configurable options
Usable as inputs, open-drain or push-pull outputs
Configurable clock output for external devices
- 48 MHz to 94 kHz
Toggle LED during SMBus reads
Toggle LED during SMBus writes
Supply Voltage
Self-powered: 3.0 to 3.6 V
USB bus powered: 4.0 to 5.25 V
I/O voltage: 1.8 V to V_DD
Ordering Part Number
CP2112-F02-GM
Package
RoHS-compliant 24-pin QFN (4 x 4 mm)
Temperature Range: –40 to +85 °C
Connect to
VBUS or
External Supply
USB
Connector
VBUS
D+
D-
GND
Logic Level
Supply
(1.8V to VDD)
REGIN _Voltage
VDD _Regulator
48 MHz
Oscillator
GND
USB Interface
CP2112
SMBus
Controller
VBUS
Full-Speed Peripheral
D+
12 Mbps
Function
D-
Transceiver Controller
RST
194 Byte PROM
VPP
(Product Customization)
I/O Power and Logic Levels
VIO
I/O Power and Logic Levels
GPIO and
Suspend
Controller
Figure 1. Example System Diagram
SDA
SCL
GPIO.0_TXT
GPIO.1_RXT
GPIO.2
GPIO.3
GPIO.4
GPIO.5
GPIO.6
GPIO.7_CLK
SUSPEND
SUSPEND
To
SMBus
Slave
Devices
GPIO
Signals
Suspend
Signals
Rev. 1.2 11/13
Copyright © 2013 by Silicon Laboratories
CP2112