C8051F587 Datasheet, PDF (1/1 Pages) Silicon Laboratories – Programmable gain maximizes input signal span

C8051F587
50 MIPS, 96 kB Flash, 12-Bit ADC, 32-Pin Automotive MCU
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 25 external inputs
- ±1 LSB INL; guaranteed monotonic
- Programmable throughput up to 200 ksps
- Data-dependent windowed interrupt generator
- Programmable gain maximizes input signal span
Built-in Temperature Sensor (±3 °C)
Three Comparators
Precision Internal Voltage Reference
V_DD Monitor/Brown-out Detector
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watch-points
- Inspect/modify memory, registers, and stack
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
- Multiple power saving sleep and shutdown modes
Development Kit: C8051F580DK
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
- Up to 50 MIPS throughput
Memory
- 96 kB Flash; in-system programmable; flexible security features
- 8448 bytes data RAM (256 + 8 kB)
Digital Peripherals
- Up to 25 digital I/O; all are 5 V push-pull
- Hardware I²C, SPI™, and two UART serial ports available concurrently
- Two independent programmable 16-bit counter array with six capture/
compare modules
- Six general-purpose 16-bit counter/timers
Clock Sources
- Internal programmable ±0.5% oscillator: Up to 50 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
Ordering Part Numbers
- C8051F587-IM, 32-Pin QFN (RoHS-compliant), 5 x 5 mm²
- C8051F587-IQ, 32-Pin QFP (RoHS-compliant), 9 x 9 mm²
C2CK/RST
VREGIN
VDD
GND
VDDA
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (50 MHz)
96 kB Flash Program
Memory
256 Byte RAM
8 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0,
1,2,3,4,5
2x6
channel
PCA/WDT
Priority
Crossbar
Decoder
SPI
I2C
Crossbar Control
Analog Peripherals
Voltage
Reference _VREF
VDD
VREF
12-bit
200ksps
ADC
VDD
A VREF
M _{P0 – P3}
U
X
Temp
Sensor
GND
CP0, CP0A ₊
Comparator 0 ^-
CP2, CP2A ₊
Comparator 2 ^-
CP1, CP1A ₊
Comparator 1 ^-
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Driver
Automotive
Copyright © 2008 by Silicon Laboratories
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
11.21.2008