C8051F530A Datasheet, PDF (1/1 Pages) Silicon Laboratories – Superior performance to emulation systems using ICE-chips, target pods, and sockets

C8051F530A
25 MIPS, 8 kB Flash, 12-Bit ADC, 20-Pin Automotive MCU
Analog Peripherals
12-Bit ADC, 5 V input signal; up to 16 external inputs
- ±1 LSB INL; guaranteed monotonic
- Programmable throughput up to 200 ksps
- Data-dependent windowed interrupt generator
- Programmable gain maximizes input signal span
Built-in Temperature Sensor (±3 °C)
Programmable Comparator
Precision Internal Voltage Reference
V_DD Monitor/Brown-out Detector
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watch-points
- Inspect/modify memory, registers, and stack
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Temperature Range: –40 to +125 °C
Operating Voltage: 1.8 to 5.25 V
- Multiple power saving sleep and shutdown modes
Development Kit: C8051F530ADK
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in one or
two system clocks
- Up to 25 MIPS throughput
Memory
- 8 kB Flash; in-system programmable; flexible security features
- 256 bytes data RAM
LIN 2.1
- Master or slave operation using dedicated hardware
Digital Peripherals
- Up to 16 digital I/O; all are 5 V push-pull
- SPI™ and UART serial ports available concurrently
- Programmable 16-bit counter array with three capture/compare modules
- Three general-purpose 16-bit counter/timers
Clock Sources
- Internal programmable 0.5% oscillator: Up to 25 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
Ordering Part Numbers
- C8051F530A-IT, 20-Pin TSSOP (RoHS-compliant), 6x6 mm²
- C8051F530A-IM, 20-Pin QFN (RoHS-compliant), 4 x 4 mm²
C2CK/RST
VREGIN
VDD
GND
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (25 MHz)
8 kB Flash Program
Memory
256 Byte SRAM
Voltage Regulator
(LDO)
SFR
Bus
XTAL1
XTAL2
System Clock Setup
External Oscillator
Internal Oscillator
(±0.5%)
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2
3 Channel
PCA/WDT
Priority
Crossbar
Decoder
LIN 2.1
SPI
Crossbar Control
Analog Peripherals
VDD
Voltage
Reference _VREF
VREF
12-bit
200ksps
ADC
VDD
A
VREF
M
U
X
Temp
Sensor
GND
CP0, CP0A ₊
-
Comparator
VREGIN
Port 0
Drivers
Port 1
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/C2D
P0.7/XTAL1
P1.0/XTAL2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Automotive
Copyright © 2008 by Silicon Laboratories
11.20.2008