C8051F335 Datasheet, PDF (1/2 Pages) Silicon Laboratories – 25 MIPS, 2 kB Flash, 20-Pin Mixed-Signal MCU

C8051F335
25 MIPS, 2 kB Flash, 20-Pin Mixed-Signal MCU
Analog Peripherals
Comparator
- Programmable hysteresis and response time
- Configurable to generate interrupts or reset
- Low current (0.4 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watchpoints
- Inspect/modify memory, registers, and stack
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Supply Voltage: 2.7 to 3.6 V
- Typical operating current: 6.4 mA at 25 MHz
9 µA at 32 kHz
- Typical stop mode current: <0.1 µA
Temperature Range: –40 to +85 °C
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 768 bytes data RAM
- 2 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digital Peripherals
- 17 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
- Programmable 16-bit counter/timer array with three capture/compare
modules, WDT
- 4 general-purpose 16-bit counter/timers
- Real-time clock mode using PCA or timer and external clock source
Clock Sources
- Two internal oscillators:
-24.5 MHz, 2% accuracy supports UART operation
-80 kHz low frequency, low-power
- External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
- Can switch between clock sources on-the-fly
Package
- 20-Pin QFN (lead-free package)
Ordering Part Numbers
- C8051F335-GM
VDD
GND
RST/C2CK
Analog/Digital
Power
C2D
Debug HW
2 kB
8
FLASH
0
256 Byte
5 ^Reset
SRAM
POR
Brown-
Out
1
512 Byte
XRAM
XTAL1
XTAL2
External
Oscillator
Circuit
24.5 MHz (2%)
Internal
Oscillator
C
o SFR Bus
r
System Clock
e
80kHz
Internal
Oscillator
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI
Port 1
Latch
P
0
D
r
v
X
B
A
R
P
1
D
r
v
CP0 ₊
-
P0.0/VREF
P0.1/IDAC
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 2
Latch
C2D
P2.0/C2D
Small Form Factor
Copyright © 2005 by Silicon Laboratories
4.19.2005