C8051F314 Datasheet, PDF (1/2 Pages) Silicon Laboratories – 25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU

C8051F314
25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU
Analog Peripherals
Two Comparators
- Programmable hysteresis and response time
- Configurable to generate interrupts or reset
- Low current (0.4 µA)
POR/Brown-out Detector
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Supply Voltage: 2.7 to 3.6 V
- Typical Operating Current:7 mA at 25 MHz
15 µA at 32 kHz
- Typical Stop Mode Current: <0.1 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler
Memory
- 1280 bytes data RAM
- 8 kB Flash; in-system programmable in 512-byte sectors (512 bytes are
reserved)
Digital Peripherals
- 29 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
- Programmable 16-bit counter/timer array with five capture/compare
modules, WDT
- 4 general-purpose 16-bit counter/timers
- Realtime clock mode using timer or PCA
Clock Sources
- Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
- External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
- Can switch between clock sources on-the-fly
32-Pin LQFP
Temperature Range: –40 to +85 °C
VDD
Analog/Digital
Power
GND
RST/C2CK
XTAL1
XTAL2
C2D
Debug HW
POR
Brown-
Out
8
0
5 ^Reset
1
External
Oscillator
Circuit
2%
Internal
Oscillator
C
o
System Clock
r
e
8 kB
FLASH
256 Byte
SRAM
1 kB
XRAM
SFR Bus
Port 0
Latch
Port 1
Latch
UART
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
P
0
D
r
v
C
R
P
O
1
S
S
D
B
r
A
v
R
P
2
D
r
v
P
3
Port 3
Latch
D
r
v
CP0
+
-
CP1
+
-
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
Small Form Factor
Copyright © 2004 by Silicon Laboratories
8.26.2004