C8051F065 Datasheet, PDF (1/2 Pages) Silicon Laboratories – 25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU

C8051F065
25 MIPS, 64 kB Flash, 16-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
Two 16-Bit ADCs
- ±0.75 LSB INL; no missing codes
- Programmable throughput up to 1 Msps (each ADC)
- 1 external input each; programmable as two single-ended or one differ-
ential ADC
- DMA to XRAM or external memory interface
- Data-dependent windowed interrupt generator
Three Comparators
- 16 programmable hysteresis values
- Configurable to generate interrupts or reset
Internal Voltage Reference
Precision V_DD Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watchpoints, stack monitor
- Inspect/modify memory and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- IEEE1149.1 compliant boundary scan
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler
Memory
- 4352 bytes data RAM
- 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
Digital Peripherals
- 24 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
- Programmable 16-bit counter/timer array with six capture/compare mod-
ules
- 5 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
- Real-time clock mode using timers or PCA
Clock Sources
- Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
- External oscillator: Crystal, RC, C, or Clock
- Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
- Typical operating current: 18 mA at 25 MHz
- Multiple power saving sleep and shutdown modes
64-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDI
TDO
RST
MONEN
XTAL1
XTAL2
VREF
AVDD
ADGND
AV+
AGND
VREF0
VRGND0
AIN0
AIN0G
VBGAP0
CNVSTR0
AV+
AGND
VREF1
VRGND1
AIN1
AIN1G
VBGAP1
CNVSTR1
Digital Power
8
Analog Power
0
JTAG ^{Boundary Scan}
Logic _{Debug HW}
VDD Monitor
WDT
5
1 ^Reset
External
Oscillator
Circuit
25 MHz 2%
Internal
Oscillator
VREF
System Clock
C
o
r
e
SFR Bus
64 kB
FLASH
256 Byte
RAM
4 kB
RAM
ADC0
1 Msps _R
(16-Bit) E
S
U
L
AVDD
T
ADGND
0
External Data
Memory Bus
+
D
R^Σ
I
F
ADC1 ^E
-
F
1 Msps
S
U
(16-Bit) L
T
1
DMA
EMIF
Cntrl
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2,3,4
P0, P1,
P2, P3
Latches
P0
Drv
C
R
P1
O
Drv
S
S
B
P2
Drv
A
R
P3
Drv
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
CP0
+
-
CP1
+
-
CP2
+
-
P2.6
P2.7
P2.2
P2.3
P2.4
P2.5
P4 Latch
Ctrl Latch
P5 Latch
Addr15-8
P6 Latch
Addr7-0
P7 Latch
Data Latch
P4
DRV
P5
DRV
P6
DRV
P7
DRV
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
7.28.04