C8051F040 Datasheet, PDF (1/2 Pages) List of Unclassifed Manufacturers – CAN2.0B 64KB ISP FLASH MCU

C8051F040
25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
12-Bit ADC
- ±1 LSB INL; guaranteed monotonic
- Programmable throughput up to 100 ksps
- 13 external inputs; programmable as single-ended or differential
- Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
- Data-dependent windowed interrupt generator
- Built-in temperature sensor (±3 °C)
High-Voltage Differential Amplifier
- 60 V common mode input range
- Offset adjust from –60 to +60 V
- 16 gain settings from 0.05 to 16
8-Bit ADC
- Programmable throughput up to 500 ksps
- 8 external inputs; programmable as single-ended or differential
- Programmable amplifier gain: 4, 2, 1, 0.5
Two 12-Bit DACs
Three Comparators
Internal Voltage Reference
Precision V_DD Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
- On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
- Provides breakpoints, single stepping, watchpoints, stack monitor, pro-
gram trace memory
- Inspect/modify memory and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- IEEE1149.1 compliant boundary scan
Supply Voltage: 2.7 to 3.6 V
- Typical operating current: 10 mA at 25 MHz
- Multiple power saving sleep and shutdown modes
Temperature Range: –40 to +85 °C
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler
Memory
- 4352 bytes data RAM
- 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
- External parallel data memory interface
CAN Bus 2.0B
- 32 message objects
- ”Mailbox" implementation only interrupts CPU when needed
Digital Peripherals
- 64 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
- Programmable 16-bit counter array with 6 capture/compare modules
- 5 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
- Real-time clock mode using timer 3 or PCA
Clock Sources
- Internal programmable 2% oscillator: up to 25 MHz
- External oscillator: Crystal, RC, C, or Clock
Package
- 100-pin TQFP (standard lead and lead-free packages)
Ordering Part Numbers
- Lead-free package: C8051F040-GQ
- Standard package: C8051F040
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AV+
AGND
AGND
AGND
TCK
TMS
TDI
TDO
RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
HVAIN+
HVAIN-
HVREF
HVCAP
CAN 2.0B
Digital Power
8
Analog Power
0
5
JTAG ^{Boundary Scan}
1
Logic _{Debug HW}
Reset
VDD
Monitor
WDT
C
External
Oscillator
Circuit
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
o
System
Clock
r
e
Internal
2%
Oscillator
SFR Bus
64 kB
FLASH
32x136
CANRAM
256 byte
RAM
4 kB
XRAM
UART0
UART1
SMBus
SPI Bus
PCA
Timers
0,1,2,3,4
Port
0,1,2,3
&4
Latches
CAN
2.0B
P0
Drv
C
R
P1
O
Drv
S
S
B
P2
Drv
A
R
P3
Drv
ADC
500 ksps
Prog
Gain
(8-Bit)
CP0
+
-
+
CP1
-
+
CP2
-
A
M _8:1
U
X
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
A
M
Prog
U
Gain
X
TEMP
SENSOR
HVAMP
ADC
100 ksps
(12-Bit)
A
M
8:2
U
X
External Data Memory Bus
Port 4 <from crossbar>
Bus Control
Ctrl Latch
Address [15:0]
P5 Latch
Addr [7:0]
P6 Latch
Addr [15:8]
Data [7:0]
P7 Latch
Data Latch
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0/CPx
P2.7/CPx
P3.0/AIN0.6
P3.7/AIN0.7
CTX0
CRX0
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A0
P5.7/A7
P6.0/A8
P6.7/A15
P7.0/D0
P7.7/D7
Copyright © 2005 by Silicon Laboratories
5.5.2005