C8051F017 Datasheet, PDF (1/2 Pages) Silicon Laboratories – 25 MIPS, 32 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU

C8051F017
25 MIPS, 32 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
- ±1 LSB INL; no missing codes
- Programmable throughput up to 100 ksps
- 4 external inputs; programmable as single-ended or differential
- Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
- Data-dependent windowed interrupt generator
- Built-in temperature sensor (±3 °C)
Two 12-Bit DACs
- Voltage output
- 10 µsec settling time
Comparator
- 16 programmable hysteresis values
- Configurable to generate interrupts or reset
Internal Voltage Reference
V_DD Monitor/Brown-out Detector
On-Chip JTAG Debug
- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
- Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- Fully compliant with IEEE 1149.1 specification
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of Instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler; up to 21 interrupt sources
Memory
- 2304 bytes data RAM
- 32 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
Digital Peripherals
- 8 port I/O; all are 5 V tolerant
- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
- Programmable 16-bit counter/timer array with five capture/compare
modules
- 4 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
Clock Sources
- Internal programmable oscillator: 2–16 MHz
- External oscillator: Crystal, RC, C, or Clock
- Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
- Typical operating current: 12.5 mA at 25 MHz
- Multiple power saving sleep and shutdown modes
32-Pin LQFP
Temperature Range: –40 to +85 °C
VDD
VDD
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
RST
XTAL1
XTAL2
VREF
DAC1
DAC0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
CP0+
CP0-
Digital Power
Analog Power
JTAG ^{Boundary Scan}
Logic _{Debug HW}
VDD
Monitor
WDT
8
0
5 ^Reset
1
External
Oscillator
Circuit
Internal
Oscillator
C
o ^{System Clock}
r
e
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
A
M
Prog
U
Gain
X
CP0
TEMP
SENSOR
CP1
ADC
100 ksps
(10-Bit)
32 kB
FLASH
256 Byte
RAM
2048 Byte
XRAM
SFR Bus
UART
C
SMBus
R
SPI Bus
O
S
5-Chnl
PCA
S
B
Timers
A
0,1,2
R
Timer 3
S
Port 0
Latch
W
I
Port 1
Latch
T
C
Port 2
Latch
H
Port 3
Latch
Precision Mixed Signal
Copyright © 2004 by Silicon Laboratories
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P0.0
P0.1
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P0.2
P0.3
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P0.4
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P0.5
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P0.6
P0.7
P
1
D
r
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P
2
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P
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6.15.2004