AN82 Datasheet, PDF (1/4 Pages) Silicon Laboratories – HIGH-DENSITY MULTI CHANNEL OC-48 LAYOUT GUIDELINES FOR THE Si5100 AND Si5110

AN82
HIGH-DENSITY MULTI CHANNEL OC-48 LAYOUT GUIDELINES FOR THE
Si5100 AND Si5110
Introduction
OC-48 small form-factor hot-pluggable modules (SFP)
allow designers to place a large number of OC-48 links
in a relatively small amount of space. As the density
increases, adjacent channels are more likely to interfere
with each other. When the Si5110 or Si5100 OC-48
transceivers are used to receive and transmit through
the SFP module, it is necessary to minimize the
adjacent channel coupling in order to meet the transmit
jitter generation requirements.
Background
The oscillator that generates the timing for the transmit
data within the transceiver stores energy in electric and
magnetic fields during oscillation. The magnetic fields
extend several inches (centimeters) from the device but
decrease in magnitude at a rate inversely proportional
to the square of the distance. Consequently, distance is
key to minimizing the adjacent channel coupling.
In addition, energy from other sources can couple into
the device through capacitive and mutually-inductive
means. These paths effectively reduce the distance that
an adjacent carrier appears.
Most materials do not provide any change in the
permeability of the region at RF and microwave
frequencies (Refer to Noise Reduction Techniques in
Electronic Systems, 2nd Edition 1988, pp182–7 by
Henry W. Ott). The most notable exception is metal.
Completely surrounding magnetic fields with sufficiently
thick metal isolates the fields.
Layout Guidelines
The following layout guidelines are based on results
obtained from an experimental board as well as general
best-practice layout principles. The implementation of
these recommendations should be straightforward.
Adjacent Channel Traces
(High-Speed and TTL)
Since the magnetic fields extend beyond the transceiver
device, mutual inductance exists between the oscillator
and the surrounding metal (traces, power planes, heat-
sinks, etc.). To minimize the effect of switching currents
from both TTL and high-speed I/O, these traces should
be run on stripline layers. With a stripline structure, at
least one power plane will isolate the traces from the
oscillator's magnetic fields, thereby reducing the
coupling.
In addition, adjacent devices can couple to surrounding
devices if their TTL or high-speed traces can couple to
each other. Since PCB fabrication does not allow for
solid walls perpendicular to the plane of the board, a
"wall" of vias can be used to isolate nearby traces as
shown in Figure 1. Vias should be placed along the axis
of propagation no farther than 100 mil apart.
Diff Pair
Via Wall
Diff Pair
Gnd
Planes
Magnetic
Field Lines
Figure 1. Stripline Via Wall Isolation
Power Supply Isolation (1.8 V and 3.3 V)
The oscillator within the transceiver relies on a clean
power supply to provide very low generated jitter. Noise/
interference from adjacent ICs couples electrically
through the power planes. Each transceiver device
should operate on a separate power island for both the
1.8 V and 3.3 V supplies. Ferrite beads should be used
to isolate the islands as shown in Figure 2.
VDD VDDIO
Si5110 Si5110 Si5110
Si5110
GND
Figure 2. Power Supply Isolation
Rev. 0.1 6/03
Copyright © 2003 by Silicon Laboratories
AN82-DS01