AN699 Datasheet, PDF(1/6 Page) Silicon Laboratories – FPGA REFERENCE CLOCK PHASE JITTER SPECIFICATIONS

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AN699 Datasheet, PDF (1/6 Pages) Silicon Laboratories – FPGA REFERENCE CLOCK PHASE JITTER SPECIFICATIONS

AN699

FPGA REFERENCE CLOCK PHASE JITTER SPECIFICATIONS

1. Introduction

Driven by market demand for ever-increasing network bandwidth, high-speed digital communications equipment

manufacturers look to communication semiconductor suppliers for the latest in high-speed standards-based digital

communications protocol building blocks. Several Field Programmable Gate Array (FPGA) vendors have taken up

this challenge and produced products specifically targeted to various segments of high-speed serial digital

communications designs. As a result, communications and embedded computing product designs are increasingly

utilizing FPGAs with embedded serializer-deserializers (SerDes) for critical high-speed transceiver and serial

protocol processing. Within high-speed serial digital communications, controlling, reducing, and maintaining low

signal path jitter is a paramount concern, especially as bit rates increase into the multi-gigabit realm and beyond.

FPGA vendors and system designers alike have become increasingly aware that low jitter digital communications

absolutely requires low or ultra-low jitter clocks. Silicon Labs timing solutions can easily meet the low jitter clocking

requirements for high-speed serial digital communications.

2. FPGA Clock Jitter Requirements

The vast majority of the FPGA market share is split between two companies, Xilinx and Altera. These two

companies have FPGA products that specifically address various high-speed serial digital communications market

segments. As a result of this market focus, these FPGA companies have published specifications for input

reference clock jitter requirements that allow their FPGA based products to implement spec-compliant serial digital

communications protocols. Although clock jitter can be specified in different forms, the almost universally accepted

format for high-speed serial digital communications links is that of a phase noise (jitter) mask in the frequency

domain. (For an excellent technical explanation of jitter and phase noise, refer to Silicon Labsâ application note

âAN687: A Primer on Jitter, Jitter Measurement and Phase-Locked Loopsâ.) Tables 1 and 2 provide the input

reference clock jitter specifications published by the two main FPGA vendors for FPGA products targeted for use in

high-speed serial digital communications. In addittion to these jitter requirements,Table 1 and Table 2 also provide

the jitter specifications for a selection of Silicon Labsâ timing devices. The selected devices include the Si51x 0.1â

250 MHz programmable XO, Si53x/Si570 10â1417 MHz programmable XO, the Si5338 any frequency, any-output

clock generator, and the Si5326/68 any-frequency jitter attenuating clock. As shown in the following tables, the

specified Silicon Labs timing devices easily meet or exceed the FPGAâs input reference clock jitter requirements

with substantial margin and are well suited for use in high-speed digital serial communications applications.

Rev. 0.1 7/12

AN699

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