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AN611
USING THE ISOVOLT DC/DC CONVERTER
REFERENCE DESIGN
1. Design Overview
The ISOvolt isolated dc/dc reference design shown in Figure 1 is a low-cost, robust, isolated dc/dc converter
capable of delivering a maximum of 3 W of output power. This isolated power converter enables Silicon Labs’
isolation products to be powered from a single bias supply, eliminating the need for separate supplies on both sides
of the isolation device. This design features fold-back current limiting and thermal shutdown protection, low EMI
operation, and high (78%) operating efficiency. Input voltage ranges are 3.3 or 4.5 Vdc to 5.5 Vdc and generate
isolated output voltages of 3.3, 5.0, 7.0, or 24 V, depending on the transformer and output regulator used. Referring
to Figure 1, the ISOvolt reference design is based on push-pull switching topology. The timing generator is a
CT600-PX0624GM MCU, which has been factory-programmed to generate primary-side transformer switch timing.
VIN+
(P1)
7Vdc
MAX
VIN‐
(P2)
8
/RST
R17
100K
C14
X7R
4.7uF
R9 ^VIN+
220
J3
C4
470pF
TP11 _R12
P0.4 ⁶
U2
3.3V
1
VIN
VOUT ²
3 _VDD
C2
0.1
C1
10uF
XC6215P
C3
0.1uF
Ceramic
U1
C8051T600‐GM
NPO
2
0.0
1
Q1 _TP8
3
3
1 Q3
TP6
R2
1.0K
1
3
Q2
2
R10
2
1.0 _R5
200K
C8
NOPOP
VSS
3
R7
200K
C5
470pF
NPO
Input Regulator
High‐Side Driver
R6 ^VIN+
220
C6
P0.3 ⁵
470pF
NPO
2
1 ^Q4 TP3
3
TP5
3
1 Q6
GND
11
TP12
R3
1.0K ₁
3
Q5
2
R4
2
1.0 _R11
200K
Timing Generator
R1
200K
C7
470pF
NPO
Low‐Side Driver
T1
XFMR
D1
1
8
3,2
7,6
D2
4
5
TP13
TP14
1 _VIN
u4
5
VOUT
R18
8.25K
D3
XC6220B
R19
100
3 _CE
VSS
C11
X5R
10uF
C10
10uF
Q8
2
R20
10K
Output Regulator
VOUT+
(P3)
VOUT‐
(P4)
Rectifiers and Active Clamp
VIN+
C12
1uF
J1
*R12‐R15 = 100
R13*
R14
R15
U3
Si8641BB
1 _VDD1
VDD2 ¹⁶
2 _GND1
3 _A1
GND2 ¹⁵
B1 ¹⁴
4 _A2
5
A3
6 _A4
7 _EN/NC
8 _GND1
B2 ¹³
12
B3
B4 ¹¹
EN/NC2 ¹⁰
GND2 ⁹
R6
0.0
R16
VOUT+
C13
1uF
J2
Digital Isolator
Figure 1. ISOvolt Isolated DC/DC Block Diagram
This MCU has a maximum bias voltage of 3.3 V, allowing applications having 2.7 V < VIN < 3.3 V dc. Higher values
of VIN require the addition of input regulator (U2). The timing generator outputs are conditioned by high and low-
side gate driver circuits, which drive the switches on transformer T1's primary at a frequency of 500 kHz. The
resulting ac voltage on the secondary-side is rectified by a full-wave Schottky diode circuit and filtered by a bulk
capacitor (C10). An active clamp circuit sinks current during light output loads (50 mA or less) to ensure the dc
voltage stays below the maximum input voltage value of the linear output regulator. The resulting conditioned dc
voltage is regulated by a linear output regulator (U4).
The ISOvolt reference design board (see Figure 4) also contains digital isolator U3 (Silicon Labs’ Si864IBC with
three forward channels and one reverse channel) for customer use. The combination of ISOvolt and the onboard
isolator is useful in applications, such as isolated serial ports. The user can connect external signals to input blocks
J1 and J2, and VOUT+ supplies bias to the output side of the isolator.
Note: U3 maximum VDD2 is 5.5 V. If VDD2 exceeds 5 V, the value of resistor R6 must be increased to ensure that U3 pin 16
does not exceed 5.5 V under any operating conditions. For BOM, schematic, and layout details, see the “Discrete ISO-
volt Isolated DC-DC Converter Reference Design Users Guide”.
Rev. 0.2 9/11
Copyright © 2011 by Silicon Laboratories
AN611