AN575 Datasheet, PDF (1/8 Pages) STMicroelectronics – CALCULATION OF TRANSIL APPARENT DYNAMIC RESISTANCE

AN575
INTRODUCTION TO FPGA-BASED ADPLLS
1. Introduction
1.1. FPGA Approach to Electronics
System architects and board designers must constantly trade off costs, development time, performance, and
supportability. Field Programmable Gate Arrays (FPGAs) are programmable ICs that give the designer many of the
advantages of a highly integrated digital IC without the NRE costs and fabrication time of a custom digital ASIC.
The general functional flexibility of FPGAs invites their consideration in communications, control, and test
applications where different standards or data rates may need to be supported by the same hardware.
Likewise, the frequency flexibility of programmable oscillators such as the Silicon Labs Si514, Si570, and Si598
frequently lands them on the same boards where they are used as independent asynchronous oscillators.
However, these programmable oscillators can also be placed under FPGA control to implement a particular form of
highly configurable Phase Locked Loop. This application note is intended to serve as a brief introduction to this
approach and its advantages.
1.2. Taxonomy of PLLs
Phase Locked Loops or PLLs are electronic feedback circuits which lock an output signal’s phase relative to an
input reference signal’s phase. The signals of interest may be any periodic waveform, but are typically sinusoids or
digital clocks. These circuits are widely used in communications, computers, control, and measurement
applications for frequency synthesis, clock and data recovery, clock distribution, and other more specialized
functions.
PLLs are typically divided into the broad categories listed in Table 1, and are described following Roland Best’s
terminology (1997). The hardware PLLs may be implemented in discrete or integrated technology. Software PLLs
will not be described in this application note other than to state that SPLLs can mimic any of the hardware PLLs,
provided there is sufficient sampling, and the instructions can be executed fast enough for the application.
PLL
Category
LPLL
(Linear PLL)
DPLL
(Digital PLL)
ADPLL
(All Digital PLL)
SPLL
(Software PLL)
Table 1. General PLL Categories
Phase Detector Phase Error Signal
Analog
Analog
Digital
Analog
Digital
Digital
Software
Software
Loop Filter
Analog
Analog
Digital
Software
Linear (or analog) PLLs use analog 4-quadrant multipliers, such as mixers, as phase detectors. LPLLs are often
used for frequency translation and are therefore found in frequency synthesizers, radios, and phase noise
instrumentation.
The most common PLL in use today is the classic Digital PLL, so-called due to its use of a digital phase detector.
However, these circuits typically follow the digital phase detector with a charge pump whose output is converted to
an analog voltage phase error signal. This analog phase error signal is then filtered and applied to a Voltage
Controlled Oscillator (VCO). A better description might be to refer to this version as a mixed signal or charge pump
PLL. Classic DPLLs and LPLLs have generally been preferred for high-performance (low phase noise), high
Rev. 0.1 3/11
Copyright © 2011 by Silicon Laboratories
AN575